📄 a8255tb1.vhd
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-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Mode 1, Port A out, B in and check Port C Status
WriteReg(ControlReg, x"A6");
WriteReg(ChangeBit, x"0F"); -- Set Port C (7)
WriteReg(ChangeBit, x"02"); -- Reset Port C (1)
WriteReg(ChangeBit, x"00"); -- Reset Port C (0)
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Load Port output registers
WriteReg(PortA, x"11");
-- Read all ports
ReadReg(PortB, x"11");
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"0D"); -- Set Port A Int Enable (Port C (6))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"C4"); -- Read Port C Status (OBFA, INTEA, and INTEB are set)
WriteReg(PortA, x"88");
ReadReg(PortC, x"C7"); -- Read Port C Status (everything but INTA is set)
ReadReg(PortB, x"88");
ReadReg(PortC, x"CC"); -- Read Port C Status
-- Load Port output registers to bring down INTA
WriteReg(PortA, x"00");
-- REVERSE LOOPBACK DIRECTION
-- Set Loop Back Mode
LoopBackMode <= Mode1_BToA;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Mode 1, Port A out, B in and check Port C Status
WriteReg(ControlReg, x"B4");
WriteReg(ChangeBit, x"0E"); -- Reset Port C (7)
WriteReg(ChangeBit, x"0C"); -- Reset Port C (6)
WriteReg(ChangeBit, x"0A"); -- Reset Port C (5)
WriteReg(ChangeBit, x"08"); -- Reset Port C (4)
WriteReg(ChangeBit, x"06"); -- Reset Port C (3)
WriteReg(ChangeBit, x"04"); -- Reset Port C (2)
WriteReg(ChangeBit, x"03"); -- Set Port C (1)
WriteReg(ChangeBit, x"00"); -- Reset Port C (0)
ReadReg(PortC, x"02"); -- Read Port C Status (only OBFB is set)
-- Load Port output registers
WriteReg(PortB, x"33");
-- Read all ports
ReadReg(PortA, x"33");
ReadReg(PortC, x"02"); -- Read Port C Status (only OBFB is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"09"); -- Set Port A Int Enable (Port C (4))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"16"); -- Read Port C Status (OBFA, INTEA, and INTEB are set)
WriteReg(PortB, x"44");
ReadReg(PortC, x"3E"); -- Read Port C Status (everything but INTB is set)
ReadReg(PortA, x"44");
ReadReg(PortC, x"17"); -- Read Port C Status (INTB and OBFB set)
-- Load Port output registers to bring down INTB
WriteReg(PortB, x"FF");
------------------------------------------------------------
------------------------------------------------------------
ASSERT false REPORT "START MODE 2 TEST" SEVERITY NOTE;
-- Set Loop Back Mode
LoopBackMode <= Mode2_AToB;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Port A to Mode 2, B in and check Port C Status
WriteReg(ControlReg, x"C6");
WriteReg(ChangeBit, x"0F"); -- Set Port C (7) --OBFA
WriteReg(ChangeBit, x"0C"); -- Reset Port C (6) --INTE1
WriteReg(ChangeBit, x"0A"); -- Reset Port C (5) --IBFA
WriteReg(ChangeBit, x"08"); -- Reset Port C (4) --INTE2
WriteReg(ChangeBit, x"06"); -- Reset Port C (3) --INTRA
WriteReg(ChangeBit, x"04"); -- Reset Port C (2) --INTEB
WriteReg(ChangeBit, x"02"); -- Reset Port C (1) --IBFB
WriteReg(ChangeBit, x"00"); -- Reset Port C (0) --INTRB
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Load Port output registers
WriteReg(PortA, x"11");
-- Read all ports
ReadReg(PortB, x"11");
ReadReg(PortC, x"80"); -- Read Port C Status (only OBFA is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"0D"); -- Set Port A Int Enable (Port C (6))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"C4"); -- Read Port C Status (OBFA, INTEA, and INTEB are set)
WriteReg(PortA, x"88");
ReadReg(PortC, x"C7"); -- Read Port C Status (everything but INTA is set)
ReadReg(PortB, x"88");
ReadReg(PortC, x"CC"); -- Read Port C Status
-- Load Port output registers to bring down INTA
WriteReg(PortA, x"00");
-- Set Loop Back Mode
LoopBackMode <= Mode2_BToA;
-- Reset chip and set inputs to default values
InitInputsAndReset;
-- Read Control Reg after reset
ReadReg(ControlReg, x"9B"); -- Resets to Mode 0, all inputs
-- Set Port A to Mode 2, B out and check Port C Status
WriteReg(ControlReg, x"C4");
WriteReg(ChangeBit, x"0F"); -- Set Port C (7) --OBFA
WriteReg(ChangeBit, x"0C"); -- Reset Port C (6) --INTE1
WriteReg(ChangeBit, x"0A"); -- Reset Port C (5) --IBFA
WriteReg(ChangeBit, x"08"); -- Reset Port C (4) --INTE2
WriteReg(ChangeBit, x"06"); -- Reset Port C (3) --INTRA
WriteReg(ChangeBit, x"04"); -- Reset Port C (2) --INTEB
WriteReg(ChangeBit, x"03"); -- Set Port C (1) --OBFB
WriteReg(ChangeBit, x"00"); -- Reset Port C (0) --INTRB
ReadReg(PortC, x"82"); -- Read Port C Status (OBFA, OBFB is set)
-- Load Port output registers
WriteReg(PortB, x"66");
-- Read all ports
ReadReg(PortA, x"66");
ReadReg(PortC, x"82"); -- Read Port C Status (only OBFA is set)
-- Do same test with interrupt enables on
WriteReg(ChangeBit, x"09"); -- Set Port A Int Enable (Port C (4))
WriteReg(ChangeBit, x"05"); -- Set Port B Int Enable (Port C (2))
ReadReg(PortC, x"96"); -- Read Port C Status (OBFA, INTEA2, and INTEB are set)
WriteReg(PortB, x"88");
ReadReg(PortC, x"BE"); -- Read Port C Status (everything but INTRB is set)
ReadReg(PortA, x"88");
ReadReg(PortC, x"97"); -- Read Port C Status
-- Load Port output registers to bring down INTA
WriteReg(PortB, x"00");
ASSERT false REPORT "END OF TEST" SEVERITY NOTE;
WAIT;
END PROCESS GeneralStimulus;
------------------------------------------------------------
-- Process to loop PA to PB, and PC upper to PC lower
------------------------------------------------------------
OutputBufferPrc : Process (PAEN_Resp, PBEN_Resp, PCEN_Resp, PAOUT_Resp, PBOUT_Resp, PCOUT_Resp)
BEGIN
IF (PAEN_Resp = '1') THEN
PA <= PAOUT_Resp AFTER LoopDelay;
ELSE
PA <= "ZZZZZZZZ" AFTER LoopDelay;
END IF;
IF (PBEN_Resp = '1') THEN
PB <= PBOUT_Resp AFTER LoopDelay;
ELSE
PB <= "ZZZZZZZZ" AFTER LoopDelay;
END IF;
FOR I IN 0 TO 7 LOOP
IF (PCEN_Resp(I) = '1') THEN
PC(I) <= PCOUT_Resp(I) AFTER LoopDelay;
ELSE
PC(I) <= 'Z' AFTER LoopDelay;
END IF;
END LOOP;
END PROCESS OutputBufferPrc;
-- -- Output buffer assignments
PAIN_Stim <= PA;
PBIN_Stim <= PB;
PCIN_Stim <= PC;
-- Loop back assignments
LoopBackPrc : Process (LoopBackMode, PA, PB, PC)
BEGIN
PAIN_Stim <= PB ;
PBIN_Stim <= PA ;
IF (LoopBackMode = Mode0) THEN
PCIN_Stim (7 DOWNTO 4) <= PC (3 DOWNTO 0) ;
PCIN_Stim (3 DOWNTO 0) <= PC (7 DOWNTO 4) ;
ELSIF (LoopBackMode = Mode1_BToA) THEN
PCIN_Stim (7) <= PC (7) ;
PCIN_Stim (6) <= PC (6) ;
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (4) <= PC (1) ; -- OBFB to STBA
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (2) <= NOT PC (5) ; -- IBFA to ACKB
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (0) <= PC (0) ;
ELSIF (LoopBackMode = Mode2_BToA) THEN
PCIN_Stim (7) <= PC (7) ;
PCIN_Stim (6) <= '1';
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (4) <= PC (1) ; -- OBFB to STBA
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (2) <= NOT PC (5) ; -- IBFA to ACKB
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (0) <= PC (0) ;
ELSIF (LoopBackMode = Mode1_AToB) THEN
PCIN_Stim (0) <= PC (0) ;
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (2) <= PC (7) ; -- OBFA to STBB
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (4) <= PC (4) ;
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (6) <= NOT PC (1) ; -- IBFB to ACKA
PCIN_Stim (7) <= PC (7) ;
ELSIF (LoopBackMode = Mode2_AToB) THEN
PCIN_Stim (0) <= PC (0) ;
PCIN_Stim (1) <= PC (1) ;
PCIN_Stim (2) <= PC (7) ; -- OBFA to STBB
PCIN_Stim (3) <= PC (3) ;
PCIN_Stim (4) <= '1';
PCIN_Stim (5) <= PC (5) ;
PCIN_Stim (6) <= NOT PC (1) ; -- IBFB to ACKA
PCIN_Stim (7) <= PC (7) ;
END IF;
END PROCESS LoopBackPrc;
END MainTest;
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