a8255tb1.vhd

基于VHDL的8255可编程并行扩展接口芯片设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY a8255tb1 IS
  GENERIC (
          CLKOffset  : TIME :=  0 ns;
          CLKPeriod  : TIME := 200 ns;
          LoopDelay  : TIME :=  50 ns
          );
  PORT (
      RESET_Stim : OUT std_logic;
      CLK_Stim  : OUT std_logic;
      nCS_Stim  : OUT std_logic;
      nRD_Stim  : OUT std_logic;
      nWR_Stim  : OUT std_logic;
      A_Stim    : OUT std_logic_vector (1 DOWNTO 0);
      DIN_Stim  : OUT std_logic_vector (7 DOWNTO 0);
      PAIN_Stim  : OUT std_logic_vector (7 DOWNTO 0);
      PBIN_Stim  : OUT std_logic_vector (7 DOWNTO 0);
      PCIN_Stim  : OUT std_logic_vector (7 DOWNTO 0);

      DOUT_Resp  : IN std_logic_vector (7 DOWNTO 0);
      PAOUT_Resp : IN std_logic_vector (7 DOWNTO 0);
      PAEN_Resp  : IN std_logic;
      PBOUT_Resp : IN std_logic_vector (7 DOWNTO 0);
      PBEN_Resp  : IN std_logic;
      PCOUT_Resp : IN std_logic_vector (7 DOWNTO 0);
      PCEN_Resp  : IN std_logic_vector (7 DOWNTO 0)
      );
END a8255tb1;

-----------------------------
-- Architecture Body
-----------------------------
ARCHITECTURE MainTest OF a8255tb1 IS

SIGNAL PA : std_logic_vector (7 DOWNTO 0);
SIGNAL PB : std_logic_vector (7 DOWNTO 0);
SIGNAL PC : std_logic_vector (7 DOWNTO 0);

TYPE LoopBackModeType IS (Mode0, Mode1_AToB, Mode1_BToA, Mode2_AToB, Mode2_BToA);
SIGNAL LoopBackMode : LoopBackModeType;

BEGIN


  CLKClockPrc : PROCESS
    BEGIN
    CLK_Stim <= '0';
    WAIT FOR CLKOffset;
    LOOP
      CLK_Stim <= '0';
      WAIT FOR CLKPeriod/2;
      CLK_Stim <= '1';
      WAIT FOR CLKPeriod/2;
    END LOOP;
  END PROCESS CLKClockPrc;

  GeneralStimulus : PROCESS
    CONSTANT  PortA      : std_logic_vector(1 DOWNTO 0) := "00";
    CONSTANT  PortB      : std_logic_vector(1 DOWNTO 0) := "01";
    CONSTANT  PortC      : std_logic_vector(1 DOWNTO 0) := "10";
    CONSTANT  ControlReg : std_logic_vector(1 DOWNTO 0) := "11";
    CONSTANT  ChangeBit  : std_logic_vector(1 DOWNTO 0) := "11";

    -----------------------------------------------------------------------
    -- Define procedure to initialize inputs to default values and reset
    -----------------------------------------------------------------------
    PROCEDURE InitInputsAndReset IS
      BEGIN
        nCS_Stim  <= '1';
        nRD_Stim  <= '1';
        nWR_Stim  <= '1';
        A_Stim    <= "00";
        DIN_Stim  <= "00000000";

        RESET_Stim <= '1';
        WAIT FOR CLKPeriod * 2;
        RESET_Stim <= '0';
        WAIT FOR CLKPeriod * 2;
          
    END InitInputsAndReset;

    -----------------------------------------------------------------------
    -- Define procedure to read any register and compare to an expected value
    -----------------------------------------------------------------------
    PROCEDURE  ReadReg (Address      : IN std_logic_vector(1 DOWNTO 0);
                        ExpectedData : IN bit_vector(7 DOWNTO 0)
                        ) IS
      BEGIN
        A_Stim <= Address;
        WAIT FOR CLKPeriod;

        nCS_Stim <= '0';
        nRD_Stim <= '0';
        WAIT FOR CLKPeriod;

        ASSERT (DOUT_Resp = to_stdlogicvector(ExpectedData)) 
            REPORT "Read Data does not match Expected Data" SEVERITY WARNING;

        nCS_Stim <= '1';
        nRD_Stim <= '1';
        WAIT FOR CLKPeriod;
            
      END ReadReg;

    -----------------------------------------------------------------------
    -- Define procedure to write any register
    -----------------------------------------------------------------------
    PROCEDURE  WriteReg(Address  : IN std_logic_vector(1 DOWNTO 0);
                        Data    : IN bit_vector(7 DOWNTO 0)
                        ) IS
      BEGIN

        A_Stim <= Address;
        nCS_Stim <= '0';
        DIN_Stim <= to_stdlogicvector(Data); 
        WAIT FOR CLKPeriod;


        nWR_Stim <= '0';
        WAIT FOR CLKPeriod;

        nWR_Stim <= '1';
        WAIT FOR CLKPeriod * 2;

        nCS_Stim <= '1';
        WAIT FOR CLKPeriod * 2;
            
      END  WriteReg;


    ---------------------------------------------------------------
    -- Main Test Program
    ---------------------------------------------------------------
    BEGIN

      ASSERT false REPORT "START MODE 0 TEST" SEVERITY NOTE;

      -- Set Loop Back Mode
     LoopBackMode <= Mode0;

      -- Reset chip and set inputs to default values
      InitInputsAndReset;

      -- Read Control Reg after reset
      ReadReg(ControlReg,  x"9B");    -- Resets to Mode 0, all inputs

      -- Load Port output registers before changing mode and direction
     WriteReg(PortA, x"AA");
     WriteReg(PortB, x"55");
     WriteReg(PortC, x"F0");

     -- Set Mode 0, Port A out, B in, C upper in, C lower out
     WriteReg(ControlReg,  x"8A");

      -- Read all ports
      ReadReg(PortA,  x"AA");
      ReadReg(PortB,  x"AA");
      ReadReg(PortC,  x"00");

     -- Set Mode 0, Port A in, B out, C upper out, C lower in
      WriteReg(ControlReg,  x"98");
      WriteReg(ControlReg,  x"91");

      -- Read all ports
      ReadReg(PortA,  x"55");
      ReadReg(PortB,  x"55");
      ReadReg(PortC,  x"FF");

      -- Load Port output registers with inverse
     WriteReg(PortA, x"55");
     WriteReg(PortB, x"AA");
     WriteReg(PortC, x"0F");

      -- Read all ports
      ReadReg(PortA,  x"AA");
      ReadReg(PortB,  x"AA");
      ReadReg(PortC,  x"00");

     -- Set Mode 0, Port A out, B in, C upper out, C lower in
      WriteReg(ControlReg,  x"83");

      -- Read all ports
      ReadReg(PortA,  x"55");
      ReadReg(PortB,  x"55");
      ReadReg(PortC,  x"00");

     -- Test Port C Upper Set/Reset Bit Feature
      WriteReg(ChangeBit,  x"09");     -- Set Port C (4)
      ReadReg(PortC,  x"11");

      WriteReg(ChangeBit,  x"0B");  -- Set Port C (5)
      ReadReg(PortC,  x"33");

      WriteReg(ChangeBit,  x"0D");  -- Set Port C (6)
      ReadReg(PortC,  x"77");

      WriteReg(ChangeBit,  x"0F");  -- Set Port C (7)
      ReadReg(PortC,  x"FF");

      WriteReg(ChangeBit,  x"08");     -- Reset Port C (4)
      ReadReg(PortC,  x"EE");

      WriteReg(ChangeBit,  x"0A");  -- Reset Port C (5)
      ReadReg(PortC,  x"CC");

      WriteReg(ChangeBit,  x"0C");  -- Reset Port C (6)
      ReadReg(PortC,  x"88");

      WriteReg(ChangeBit,  x"0E");  -- Reset Port C (7)
      ReadReg(PortC,  x"00");

     -- Set Mode 0, Port A out, B in, C upper in, C lower out
      WriteReg(ControlReg,  x"8A");
     WriteReg(PortC, x"00");

     -- Test Port C Lower Set/Reset Bit Feature
      WriteReg(ChangeBit,  x"01");     -- Set Port C (0)
      ReadReg(PortC,  x"11");

      WriteReg(ChangeBit,  x"03");  -- Set Port C (1)
      ReadReg(PortC,  x"33");

      WriteReg(ChangeBit,  x"05");  -- Set Port C (2)
      ReadReg(PortC,  x"77");

      WriteReg(ChangeBit,  x"07");  -- Set Port C (3)
      ReadReg(PortC,  x"FF");

      WriteReg(ChangeBit,  x"00");     -- Reset Port C (0)
      ReadReg(PortC,  x"EE");

      WriteReg(ChangeBit,  x"02");  -- Reset Port C (1)
      ReadReg(PortC,  x"CC");

      WriteReg(ChangeBit,  x"04");  -- Reset Port C (2)
      ReadReg(PortC,  x"88");

      WriteReg(ChangeBit,  x"06");  -- Reset Port C (3)
      ReadReg(PortC,  x"00");

------------------------------------------------------------
------------------------------------------------------------
      ASSERT false REPORT "START MODE 1 TEST" SEVERITY NOTE;

      -- Set Loop Back Mode
     LoopBackMode <= Mode1_AToB;