📄 __projnav.log
字号:
Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal data_out cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.ERROR:HDLParsers:164 - G:/FPJA/MyFPJA/my_sram.vhd Line 27. parse error, unexpected CLOSEPAR, expecting IDENTIFIER or STRING_LITERALERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).Entity <my_sram> analyzed. Unit <my_sram> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <my_sram>. Related source file is G:/FPJA/MyFPJA/my_sram.vhd. Found 8-bit register for signal <data_out>. Found 8-bit 8-to-1 multiplexer for signal <$n0011> created at line 45. Found 64-bit register for signal <data>. Found 64 1-bit 2-to-1 multiplexers. Summary: inferred 72 D-type flip-flop(s). inferred 72 Multiplexer(s).Unit <my_sram> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 9 8-bit register : 9# Multiplexers : 9 8-bit 2-to-1 multiplexer : 8 8-bit 8-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *==================================================================================================================================================* Final Report *=========================================================================Completed process "View RTL Schematic".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).Entity <my_sram> analyzed. Unit <my_sram> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <my_sram>. Related source file is G:/FPJA/MyFPJA/my_sram.vhd. Found 8-bit register for signal <data_out>. Found 8-bit 8-to-1 multiplexer for signal <$n0011> created at line 45. Found 64-bit register for signal <data>. Found 64 1-bit 2-to-1 multiplexers. Summary: inferred 72 D-type flip-flop(s). inferred 72 Multiplexer(s).Unit <my_sram> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 9 8-bit register : 9# Multiplexers : 9 8-bit 2-to-1 multiplexer : 8 8-bit 8-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <my_sram> ...Loading device for application Xst from file '2s15.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block my_sram, actual ratio is 28.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s15cs144-6 Number of Slices: 58 out of 192 30% Number of Slice Flip Flops: 72 out of 384 18% Number of 4 input LUTs: 106 out of 384 27% Number of bonded IOBs: 24 out of 90 26% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clock | BUFGP | 72 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 4.180ns (Maximum Frequency: 239.234MHz) Minimum input arrival time before clock: 8.277ns Maximum output required time after clock: 6.788ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd g:\fpja\myfpja/_ngo -uc my_sram.ucf -pxc2s15-cs144-6 my_sram.ngc my_sram.ngd Reading NGO file "G:/FPJA/MyFPJA/my_sram.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "my_sram.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 40176 kilobytesWriting NGD file "my_sram.ngd" ...Writing NGDBUILD log file "my_sram.bld"...NGDBUILD done.Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Post-Translate Simulation Model".Completed process "Generate Post-Translate Simulation Model".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).INFO:Xst:1561 - G:/FPJA/MyFPJA/my_sram.vhd line 53: Mux is complete : default of case is discardedEntity <my_sram> analyzed. Unit <my_sram> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <my_sram>. Related source file is G:/FPJA/MyFPJA/my_sram.vhd. Found 8-bit register for signal <data_out>. Found 8-bit 8-to-1 multiplexer for signal <$n0011> created at line 45. Found 64-bit register for signal <data>. Found 64 1-bit 2-to-1 multiplexers. Summary: inferred 72 D-type flip-flop(s). inferred 72 Multiplexer(s).Unit <my_sram> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 9 8-bit register : 9# Multiplexers : 9 8-bit 2-to-1 multiplexer : 8 8-bit 8-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *==================================================================================================================================================* Final Report *=========⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -