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Entity <my_sram> (Architecture <behavioral>) compiled.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal mix cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.Entity <my_sram> analyzed. Unit <my_sram> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <my_sram>. Related source file is G:/FPJA/MyFPJA/my_sram.vhd.WARNING:Xst:1306 - Output <dataout> is never assigned.WARNING:Xst:647 - Input <raddr> is never used.WARNING:Xst:1780 - Signal <mix> is never used or assigned.WARNING:Xst:646 - Signal <data> is assigned but never used.Unit <my_sram> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *==================================================================================================================================================* Final Report *=========================================================================Completed process "View RTL Schematic".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.Entity <my_sram> analyzed. Unit <my_sram> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <my_sram>. Related source file is G:/FPJA/MyFPJA/my_sram.vhd.WARNING:Xst:1306 - Output <dataout> is never assigned.WARNING:Xst:647 - Input <raddr> is never used.WARNING:Xst:1780 - Signal <mix> is never used or assigned.WARNING:Xst:646 - Signal <data> is assigned but never used.Unit <my_sram> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <my_sram> ...Loading device for application Xst from file '2s15.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block my_sram, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s15cs144-6 =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View VHDL Instantiation Template".Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.Completed process "View VHDL Instantiation Template".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal data_out cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================⌨️ 快捷键说明
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