📄 __projnav.log
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Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Warning: This process is used to display the running command log file that records some application command lines. If you haven't run any process yet, this file couldn't be generated. Please run some processes to create the running command log file.
Project Navigator Auto-Make Log File-------------------------------------
Warning: This process is used to display the running command log file that records some application command lines. If you haven't run any process yet, this file couldn't be generated. Please run some processes to create the running command log file.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View VHDL Instantiation Template".Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Entity <my_sram> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.Completed process "View VHDL Instantiation Template".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.Architecture behavioral of Entity my_sram is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <my_sram> (Architecture <behavioral>).WARNING:Xst:819 - G:/FPJA/MyFPJA/my_sram.vhd line 27: The following signals are missing in the process sensitivity list: we, re.ERROR:Xst:827 - G:/FPJA/MyFPJA/my_sram.vhd line 27: Signal dataout cannot be synthesized, bad synchronous description.--> Total memory usage is 50460 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.ERROR:HDLParsers:164 - G:/FPJA/MyFPJA/my_sram.vhd Line 19. parse error, unexpected END, expecting IDENTIFIER--> Total memory usage is 48412 kilobytesERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.ERROR:HDLParsers:164 - G:/FPJA/MyFPJA/my_sram.vhd Line 19. parse error, unexpected END, expecting IDENTIFIERERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.ERROR:HDLParsers:164 - G:/FPJA/MyFPJA/my_sram.vhd Line 18. parse error, unexpected CLOSEPAR, expecting IDENTIFIERERROR: XST failedProcess "Check Syntax" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/FPJA/MyFPJA/my_sram.vhd in Library work.⌨️ 快捷键说明
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