my_sram.vhi

FPGA系统的sram的软仿真设计

-- VHDL Instantiation Created from source file my_sram.vhd -- 16:06:44 05/19/2007
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT my_sram
	PORT(
		data_in : IN std_logic_vector(7 downto 0);
		we : IN std_logic;
		re : IN std_logic;
		clock : IN std_logic;
		waddr : IN std_logic_vector(2 downto 0);
		raddr : IN std_logic_vector(2 downto 0);          
		data_out : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	Inst_my_sram: my_sram PORT MAP(
		data_in => ,
		we => ,
		re => ,
		clock => ,
		waddr => ,
		raddr => ,
		data_out => 
	);