led_control.v

基于Maxplus2的Verilog编程

module LED_control(flag,RED,YELLOW,GREEN);
output RED,YELLOW,GREEN;
input [1:0]flag;
reg RED,YELLOW,GREEN;
always @(flag)
  case(flag)
   2'b00:
     begin
      RED=1;
      YELLOW=0;
      GREEN=0;
     end
   2'b01:
     begin
      RED=0;
      YELLOW=1;
      GREEN=0;
     end
   
   2'b10:
     begin
      RED=0;
      YELLOW=0;
      GREEN=1;
     end
  endcase
endmodule