display2.v

基于Maxplus2的Verilog编程

module display2(clk,KEY1,KEY2,flag,LEDSN);
output [1:0]flag;
output [8:0]LEDSN;
input clk,KEY1,KEY2;
reg [1:0]flag;
reg [8:0]LEDSN;
parameter RED=0,YELLOW=1,GREEN=2;
integer cnt;
//initial cnt=89;
 always @(posedge clk)
 begin
 if(KEY2)
 begin
 if(KEY1)
 begin
  if(cnt>49)
   if(cnt==89)
   begin
   flag=GREEN;  
   LEDSN=40;
   cnt=cnt-1;
   end
   else 
    begin
    flag=GREEN;
    cnt=cnt-1;
    LEDSN=LEDSN-1;
    end
  else if(cnt>44)
   if(cnt==49)
   begin 
   flag=YELLOW;
   LEDSN=5;
   cnt=cnt-1;
   end
   else 
    begin
    flag=GREEN;
    cnt=cnt-1;
    LEDSN=LEDSN-1;
    end
  else if(cnt>0)
   if(cnt==44) 
    begin 
    flag=RED;  
    LEDSN=45;
    cnt=cnt-1;
    end
   else 
    begin
    flag=RED;
    cnt=cnt-1;
    LEDSN=LEDSN-1;
    end
  else cnt=89;  
 end
 else flag=RED;
 end
else cnt=89;
end
 endmodule