scc_hdlc.c

MPC850&nbsp SCC&nbsp HDLC自环通信

#include <vxworks.h>
#include <string.h>
#include "ppc860Cpm.h"
#include "ppc860Siu.h"
#include "ppc860Sio.h"
#include "scc_hdlc.h"

/* Golobal definition */
UINT32 base;
SCC_PARAM *sccpram;
hdlc_param *hdlcpram;
BDRINGS *RxTxBD;
LB *TRBuffer;
BDTRAN *SMCTxBD;

/* the entry of the program */
void main(void)
{
	base=GetIMMR();
	sccpram=(SCC_PARAM *)(base+(0x3E00));
	hdlcpram=(hdlc_param *)(base+(0x3E30));
	RxTxBD=(BDRINGS *)(base+(0x2400));
	TRBuffer=(LB *)(base+(0x2500));
	SMCTxBD=(BDTRAN *)(base+(0x2450));
     
	CC3HDLC();	
	
	SMC1Init();
}

/* get internal memory map base address */
UINT32 GetIMMR(void)
{
	__asm__(" mfspr  3,638 ");		/* baseis spr #638 */
	__asm__("rlwinm 3,3,0,0,15");
}

/* initiate SCC3 to HDLC mode */
void SCC3HDLC(void)
{
	UINT16 addr;
	*(SDCR(base)) = 0x01;
	/* Configure Port B pins to enable RXD3, TXD3. */
	*(PBPAR(base)) =0x06;
	*(PBDIR(base)) =0xFFF9;
	
	/*Enable BRGC3 ,the Baud Rate is 128k/s,with division factor 16*/
	*(BRGC3(base)) = 0x03C | 0x10000;
	
	/*Disable SCC3*/
	*(GSMR_L3(base)) &= 0xFFFFFFCF;
	
	/* - Connect SCC3 to NMSI, transmit and receive clock is BRGC3     */
	*(SICR(base)) &= ~(0x00FF0000);	/*clear SCC3*/ 
	*(SICR(base)) |= (0x00120000);
	
	addr=(UINT16) (&(RxTxBD->RxBD[0])-base);
	addr=addr-0x2000;
	
	sccpram->rbase =addr;

	addr=(UINT16) (&(RxTxBD->TxBD[0])-base);
	addr=addr-0x2000;
	sccpram->tbase =addr;
	
	sccpram->rfcr = 0x18;
	sccpram->tfcr = 0x18;
	
	sccpram->mrblr = BUFFER_SIZE;
	hdlcpram->c_mask = 0x0000F0B8;	/* 16-bit CRC-CCITT,*/
	hdlcpram->c_pres = 0x0000FFFF;
	hdlcpram->disfc = 0;
	hdlcpram->crcec = 0;  /* Clear CRC Error Counter */
	hdlcpram->abtsc = 0;  /* Clear Abort Sequence Counter */
	hdlcpram->nmarc = 0;  /* Clear Nonmatching RX Address Counter */
	hdlcpram->retrc = 0;  /* Clear Frame Re-transmission Counter */
	hdlcpram->rfthr = 1; /* Rx Frames Threshold */
	hdlcpram->mflr = 256;	/*maximum frame lenth*/
	
	/* Mask all the bits */
	hdlcpram->hmask = 0xFFFF;
	hdlcpram->haddr1 = 0x0000;
	hdlcpram->haddr2 = 0x0000;
	hdlcpram->haddr3 = STADDR;
	hdlcpram->haddr4 = 0x0000;

	InitSCCBD();
	
	InitTxBuffer();
	
	*(SCCE3(base)) = 0xFFFF;	/*clear any previous events*/
	*(SCCM3(base)) = 0x001A;	/*allow TXE, RXF, and TXB interrupts*/
	*(CIPR(base)) = 0xFFFFFFFF;	/*Clear Pending Interrupts in CIPR */

	/*one opening and one closing flag, 16-bit CCITT-CRC, and prevent multiple frames in the FIFO*/
	*(PSMR3(base)) = 0x2000;
	*(DSR3(base)) = 0x7E7E;
	
	/* Transmit FIFO length : 0 SCC3 16bytes*/
	/* Rx FIFO width : 0 SCC3 16bytes*/

	*(GSMR_H3(base)) = 0x00000000;
	/*Receiver decoding method 000 (NRZ)*/
	/*Transmit encoding method 000 (NRZ)*/
	/*MODE 0000(HDLC)*/

	*(GSMR_L3(base)) = 0x00000000;
	
	/*Diagnostic mode. 01 Local loopback mode*/
	*(GSMR_L3(base)) |= 0x00000040;

	/*Select channal SCC3,set flag,select opcode 0  (0x0081)*/
	*(CPCR(base))= 0x0081;
	
	while(*(CPCR(base))&0x0001);	

	/*Enable SCC3*/
	*(GSMR_L3(base)) |= 0x00000030;
}

/* initiate SCC Rx and Tx BD */
void InitSCCBD()
{
	int i;
	for(i=0;i<NUM_TXBDS;i++)
	{
		RxTxBD->TxBD[i].statusMode = 0x0C00;	/*Not ready,The last buffer of a frame, Transmit CRC*/
		RxTxBD->TxBD[i].dataLength = BUFFER_SIZE-2;
		RxTxBD->TxBD[i].dataPointer = TRBuffer->TxBuffer[i];
	}
	RxTxBD->TxBD[NUM_TXBDS-1].statusMode |= 0x2000; /*w=1*/
	
	for(i=0;i<NUM_TXBDS;i++)
	{
		RxTxBD->RxBD[i].statusMode = 0x9000;	/*empty,The last buffer of a frame*/
		RxTxBD->RxBD[i].dataLength = BUFFER_SIZE;
		RxTxBD->RxBD[i].dataPointer = TRBuffer->RxBuffer[i];
	}
	RxTxBD->RxBD[NUM_TXBDS-1].statusMode |= 0x2000; /*w=1*/
	return ;
}

/* initiate buffer data */
void InitTxBuffer(void)
{
	int i;
	/*Set Address*/
	for(i=0;i<NUM_TXBDS;i++)
	{
		TRBuffer->TxBuffer[i][0]=STADDR%256;
		TRBuffer->TxBuffer[i][1]=STADDR/256;
	}
	/*Initialize TxBuffer contect*/
	for(i=2;i<BUFFER_SIZE;i++)
	{
		TRBuffer->TxBuffer[0][i]=0x55;
		TRBuffer->TxBuffer[1][i]=0xaa;
		TRBuffer->TxBuffer[2][i]=i - 2;
	}
	 /*Enable transmit buffer description*/
	 RxTxBD->TxBD[0].statusMode |=0x8000;
	 RxTxBD->TxBD[1].statusMode |=0x8000;
	 RxTxBD->TxBD[2].statusMode |=0x8000;
     return ;
}

/* initiate SMC1 to UART mode */
void SMC1Init(void) 
{
	/* set SDMA's RAID */
	*MPC860_SDCR(base) = SDCR_RAID_BR5; /* set RISC arbitrator ID field to U-bus priority 5 */
    
	/* set PBPAR's SMRxD1 and SMTxD1 */
	*MPC860_PBPAR(base) |= 0xc0;			/* set pb24, 25 peripheral function */
	*MPC860_PBDIR(base) &= 0xf33f;  		/* peripheral function 0, 25 SMTXD1, 24 SMRXD1 */	
    
	/* set SIMODE's SMC1CS */
	*MPC860_SIMODE(base) = 0x00002000;      /* set to non multiple mode */
	*MPC860_SIMODE(base) &= 0xFFFF8FFF;

	*SMC_TBASE(base+ 0x3e80) = (UINT16) SMCTxBD->TxBD;	  /* set SMC1 tBD */

	/* set SMC1 Parameter RAM's TFCR */  
	*SMC_RFCR(base+ 0x3e80) = 0x10; /* ppc big endian mode */
	*SMC_TFCR(base+ 0x3e80) = 0x10; /* ppc big endian mode */

	/* set CPCR */
	*MPC860_CPCR(base) = 0x0091 ;  

	/* set UART parameter BRKLN */
	*SMC_MRBLR(base+ 0x3e80) = 1;
	*SMC_MAX_IDL(base+ 0x3e80) = 0; /*set last received break length 0*/
	*SMC_BRKEC(base+ 0x3e80) = 0;	/* */
	*SMC_BRKCR(base+ 0x3e80) = 1;	/* */

	/* Initiate SMC1 Tx BD */
	InitSMCBD();
    
	/* initial event register SMCE1 */
	*MPC860_SMCE1(base) = 0xff;

	/* initial mask register SMCM1 */
	*MPC860_SMCM1(base) =  0x17;

	/* configure CP interrup register */
	/* *MPC860_CICR(immr) = 0; */

	/* clear all pending interrupt events*/
	*MPC860_CIPR(base) = 0xffffffff;

	* initial interrupt register CIMR */
	*MPC860_CIMR(base)|= 0x10;

	/*------------------------------------*/
	/* 8-bit mode,  no parity, 1 stop-bit */
	/* UART SMC Mode							  */
	/* Normal operation (no loopback),	  */
	/* SMC Transmitter/Receiver Enabled	  */
	/*------------------------------------*/
	*MPC860_SMCMR1(base) = 0x4820;
	*MPC860_SMCMR1(base) = 0x4823;
}

/*------------------------
* Initiate SMC Tx BDs   *
*---------------------*/
void InitSMCBD(void)
{
	int i;

	/* set Tx BDs */
	for(i =0; i < 3; i++)
	{
		SMCTxBD->TxBD[i].statusMode = 0x8000;
		SMCTxBD->TxBD[i].dataLength = 256;
		SMCTxBD->TxBD[i].dataPointer = (UINT8 *)&TRBuffer->RxBuffer[i][0];
	}
	SMCTxBD->TxBD[2].statusMode = 0xa000;
}