fir321.qsf

来自「vhdl source,ver-fir-coefficient,simulink」· QSF 代码 · 共 70 行

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		fir321_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:15:49  MARCH 11, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VECTOR_WAVEFORM_FILE fir321.vwf
set_global_assignment -name VERILOG_FILE "C:/ServiceRequest/FIR/fir_compiler321/ReloadCoefficient/fir321.v"
set_global_assignment -name VERILOG_FILE "C:/ServiceRequest/FIR/fir_compiler321/ReloadCoefficient/fir321_st.v"
set_global_assignment -name VECTOR_WAVEFORM_FILE fir.vwf
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient/fir321.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient/fir321_st.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient/fir321_st_s.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient/fir321_st_u.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient/fir321_st_wr.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411/fir321.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411/fir321_st.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411/fir321_st_s.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411/fir321_st_u.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411/fir321_st_wr.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411_16/fir321.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411_16/fir321_st.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411_16/fir321_st_s.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411_16/fir321_st_u.v"
set_global_assignment -name VERILOG_FILE "C:/DesignExample/ReloadCoefficient_411_16/fir321_st_wr.v"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Stratix
set_global_assignment -name TOP_LEVEL_ENTITY fir321
set_global_assignment -name USER_LIBRARIES "C:/MegaCore/fir_compiler-v3.2.1/lib;"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE AUTO

# Simulator Assignments
# =====================
set_global_assignment -name CHECK_OUTPUTS OFF
set_global_assignment -name GLITCH_INTERVAL "1 ns"
set_global_assignment -name VECTOR_INPUT_SOURCE fir.vwf

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF