fir321.map.summary

来自「vhdl source,ver-fir-coefficient,simulink」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Fri Mar 11 15:33:58 2005
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : fir321
Top-level Entity Name : fir321
Family : Stratix
Met timing requirements : N/A
Total logic elements : 320
Total pins : 45
Total virtual pins : 0
Total memory bits : 3,201
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0