fir321_bb.v

来自「vhdl source,ver-fir-coefficient,simulink」· Verilog 代码 · 共 46 行

// Generated by FIR Compiler 3.2.1 [Altera, IP Toolbench v1.2.7 build38]
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// support information, device programming or simulation file, and any other
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// under Altera's Megafunction Partnership Program may be used only to
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module fir321 (
	clk,
	rst,
	data_in,
	coef_we,
	coef_in,
	coef_in_clk,
	fir_result,
	done,
	rdy_to_ld);

	input		clk;
	input		rst;
	input	[15:0]	data_in;
	input		coef_we;
	input	[17:0]	coef_in;
	input		coef_in_clk;
	output	[34:0]	fir_result;
	output		done;
	output		rdy_to_ld;
endmodule