fir321.v

来自「vhdl source,ver-fir-coefficient,simulink」· Verilog 代码 · 共 148 行

// megafunction wizard: %FIR Compiler v3.2.1%
// GENERATION: XML

// ============================================================
// Megafunction Name(s):
// 			fir321_st_wr
// ============================================================
// Generated by FIR Compiler 3.2.1 [Altera, IP Toolbench v1.2.7 build38]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
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module fir321 (
	clk,
	rst,
	data_in,
	coef_we,
	coef_in,
	coef_in_clk,
	fir_result,
	done,
	rdy_to_ld);


	input		clk;
	input		rst;
	input	[15:0]	data_in;
	input		coef_we;
	input	[17:0]	coef_in;
	input		coef_in_clk;
	output	[34:0]	fir_result;
	output		done;
	output		rdy_to_ld;


	fir321_st_wr	fir321_st_wr_inst(
		.clk(clk),
		.rst(rst),
		.data_in(data_in),
		.coef_we(coef_we),
		.coef_in(coef_in),
		.coef_in_clk(coef_in_clk),
		.fir_result(fir_result),
		.done(done),
		.rdy_to_ld(rdy_to_ld));
endmodule

// =========================================================
// FIR Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
// 
// Retrieval info: <?xml version="1.0"?>
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// Retrieval info:  <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.FIRModelClass"  active_core="fir321_st_wr" >
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// =========================================================