fir321.map.eqn

来自「vhdl source,ver-fir-coefficient,simulink」· EQN 代码 · 共 1,690 行 · 第 1/5 页

--N1_dffe3a[1] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|dffe3a[1]
--operation mode is normal

N1_dffe3a[1] = AMPP_FUNCTION(clk, R1_safe_q[1], VCC);


--D7_pipe[0][19] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][19]
--operation mode is normal

D7_pipe[0][19] = AMPP_FUNCTION(clk, D4_pipe[0][18], D3_pipe[0][18], VCC, D7L92);


--D6_pipe[0][19] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][19]
--operation mode is normal

D6_pipe[0][19] = AMPP_FUNCTION(clk, D2_pipe[0][18], D1_pipe[0][18], VCC, D6L92);


--D7_pipe[0][18] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][18]
--operation mode is arithmetic

D7_pipe[0][18] = AMPP_FUNCTION(clk, D4_pipe[0][18], D3_pipe[0][18], VCC, D7L72);

--D7L92 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][18]~COUT
--operation mode is arithmetic

D7L92 = AMPP_FUNCTION(D4_pipe[0][18], D3_pipe[0][18], D7L72);


--X1_q_b[9] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[9] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[9], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][17] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][17]
--operation mode is arithmetic

D7_pipe[0][17] = AMPP_FUNCTION(clk, D4_pipe[0][17], D3_pipe[0][18], VCC, D7L52);

--D7L72 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][17]~COUT
--operation mode is arithmetic

D7L72 = AMPP_FUNCTION(D4_pipe[0][17], D3_pipe[0][18], D7L52);


--X1_q_b[8] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[8] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[8], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][16] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][16]
--operation mode is arithmetic

D7_pipe[0][16] = AMPP_FUNCTION(clk, D4_pipe[0][16], D3_pipe[0][18], VCC, D7L32);

--D7L52 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][16]~COUT
--operation mode is arithmetic

D7L52 = AMPP_FUNCTION(D4_pipe[0][16], D3_pipe[0][18], D7L32);


--X1_q_b[7] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[7] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[7], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][15] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][15]
--operation mode is arithmetic

D7_pipe[0][15] = AMPP_FUNCTION(clk, D4_pipe[0][15], D3_pipe[0][15], VCC, D7L12);

--D7L32 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][15]~COUT
--operation mode is arithmetic

D7L32 = AMPP_FUNCTION(D4_pipe[0][15], D3_pipe[0][15], D7L12);


--X1_q_b[6] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[6] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[6], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][14] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][14]
--operation mode is arithmetic

D7_pipe[0][14] = AMPP_FUNCTION(clk, D4_pipe[0][14], D3_pipe[0][14], VCC, D7L91);

--D7L12 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][14]~COUT
--operation mode is arithmetic

D7L12 = AMPP_FUNCTION(D4_pipe[0][14], D3_pipe[0][14], D7L91);


--D6_pipe[0][14] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][14]
--operation mode is arithmetic

D6_pipe[0][14] = AMPP_FUNCTION(clk, D2_pipe[0][18], D1_pipe[0][18], VCC, D6L72);

--D6L92 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][14]~COUT
--operation mode is arithmetic

D6L92 = AMPP_FUNCTION(D2_pipe[0][18], D1_pipe[0][18], D6L72);


--X1_q_b[5] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[5] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[5], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][13] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][13]
--operation mode is arithmetic

D7_pipe[0][13] = AMPP_FUNCTION(clk, D4_pipe[0][13], D3_pipe[0][13], VCC, D7L71);

--D7L91 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][13]~COUT
--operation mode is arithmetic

D7L91 = AMPP_FUNCTION(D4_pipe[0][13], D3_pipe[0][13], D7L71);


--D6_pipe[0][13] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][13]
--operation mode is arithmetic

D6_pipe[0][13] = AMPP_FUNCTION(clk, D2_pipe[0][13], D1_pipe[0][18], VCC, D6L52);

--D6L72 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][13]~COUT
--operation mode is arithmetic

D6L72 = AMPP_FUNCTION(D2_pipe[0][13], D1_pipe[0][18], D6L52);


--X1_q_b[4] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[4] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[4], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][12] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][12]
--operation mode is arithmetic

D7_pipe[0][12] = AMPP_FUNCTION(clk, D4_pipe[0][12], D3_pipe[0][12], VCC, D7L51);

--D7L71 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][12]~COUT
--operation mode is arithmetic

D7L71 = AMPP_FUNCTION(D4_pipe[0][12], D3_pipe[0][12], D7L51);


--D6_pipe[0][12] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][12]
--operation mode is arithmetic

D6_pipe[0][12] = AMPP_FUNCTION(clk, D2_pipe[0][12], D1_pipe[0][18], VCC, D6L32);

--D6L52 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][12]~COUT
--operation mode is arithmetic

D6L52 = AMPP_FUNCTION(D2_pipe[0][12], D1_pipe[0][18], D6L32);


--X1_q_b[3] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[3] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[3], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][11] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][11]
--operation mode is arithmetic

D7_pipe[0][11] = AMPP_FUNCTION(clk, D4_pipe[0][11], D3_pipe[0][11], VCC, D7L31);

--D7L51 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][11]~COUT
--operation mode is arithmetic

D7L51 = AMPP_FUNCTION(D4_pipe[0][11], D3_pipe[0][11], D7L31);


--D6_pipe[0][11] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][11]
--operation mode is arithmetic

D6_pipe[0][11] = AMPP_FUNCTION(clk, D2_pipe[0][11], D1_pipe[0][11], VCC, D6L12);

--D6L32 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][11]~COUT
--operation mode is arithmetic

D6L32 = AMPP_FUNCTION(D2_pipe[0][11], D1_pipe[0][11], D6L12);


--X1_q_b[2] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[2] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[2], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][10] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][10]
--operation mode is arithmetic

D7_pipe[0][10] = AMPP_FUNCTION(clk, D4_pipe[0][10], D3_pipe[0][10], VCC, D7L11);

--D7L31 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][10]~COUT
--operation mode is arithmetic

D7L31 = AMPP_FUNCTION(D4_pipe[0][10], D3_pipe[0][10], D7L11);


--D6_pipe[0][10] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][10]
--operation mode is arithmetic

D6_pipe[0][10] = AMPP_FUNCTION(clk, D2_pipe[0][10], D1_pipe[0][10], VCC, D6L91);

--D6L12 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][10]~COUT
--operation mode is arithmetic

D6L12 = AMPP_FUNCTION(D2_pipe[0][10], D1_pipe[0][10], D6L91);


--X1_q_b[1] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[1] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[1], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][9] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][9]
--operation mode is arithmetic

D7_pipe[0][9] = AMPP_FUNCTION(clk, D4_pipe[0][9], D3_pipe[0][9], VCC, D7L9);

--D7L11 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][9]~COUT
--operation mode is arithmetic

D7L11 = AMPP_FUNCTION(D4_pipe[0][9], D3_pipe[0][9], D7L9);


--D6_pipe[0][9] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][9]
--operation mode is arithmetic

D6_pipe[0][9] = AMPP_FUNCTION(clk, D2_pipe[0][9], D1_pipe[0][9], VCC, D6L71);

--D6L91 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][9]~COUT
--operation mode is arithmetic

D6L91 = AMPP_FUNCTION(D2_pipe[0][9], D1_pipe[0][9], D6L71);


--X1_q_b[0] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[0] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_dly[0], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--D7_pipe[0][8] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][8]
--operation mode is arithmetic

D7_pipe[0][8] = AMPP_FUNCTION(clk, D4_pipe[0][8], D3_pipe[0][8], VCC, D7L7);

--D7L9 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][8]~COUT
--operation mode is arithmetic

D7L9 = AMPP_FUNCTION(D4_pipe[0][8], D3_pipe[0][8], D7L7);


--D6_pipe[0][8] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][8]
--operation mode is arithmetic

D6_pipe[0][8] = AMPP_FUNCTION(clk, D2_pipe[0][8], D1_pipe[0][8], VCC, D6L51);

--D6L71 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][8]~COUT
--operation mode is arithmetic

D6L71 = AMPP_FUNCTION(D2_pipe[0][8], D1_pipe[0][8], D6L51);


--D7_pipe[0][7] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][7]
--operation mode is arithmetic

D7_pipe[0][7] = AMPP_FUNCTION(clk, D4_pipe[0][7], D3_pipe[0][7], VCC, D7L5);

--D7L7 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][7]~COUT
--operation mode is arithmetic

D7L7 = AMPP_FUNCTION(D4_pipe[0][7], D3_pipe[0][7], D7L5);


--D6_pipe[0][7] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][7]
--operation mode is arithmetic

D6_pipe[0][7] = AMPP_FUNCTION(clk, D2_pipe[0][7], D1_pipe[0][7], VCC, D6L31);

--D6L51 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][7]~COUT
--operation mode is arithmetic

D6L51 = AMPP_FUNCTION(D2_pipe[0][7], D1_pipe[0][7], D6L31);


--D7_pipe[0][6] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][6]
--operation mode is arithmetic

D7_pipe[0][6] = AMPP_FUNCTION(clk, D4_pipe[0][6], D3_pipe[0][6], VCC);

--D7L5 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][6]~COUT
--operation mode is arithmetic

D7L5 = AMPP_FUNCTION(D4_pipe[0][6], D3_pipe[0][6]);


--D6_pipe[0][6] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][6]
--operation mode is arithmetic

D6_pipe[0][6] = AMPP_FUNCTION(clk, D2_pipe[0][6], D1_pipe[0][6], VCC, D6L11);

--D6L31 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n|pipe[0][6]~COUT
--operation mode is arithmetic