fir321.map.eqn

来自「vhdl source,ver-fir-coefficient,simulink」· EQN 代码 · 共 1,690 行 · 第 1/5 页

--Q1_q_b[9] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[9] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[9], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][17] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][17]
--operation mode is arithmetic

D9_pipe[0][17] = AMPP_FUNCTION(clk, D7_pipe[0][17], D6_pipe[0][19], VCC, D9L13);

--D9L33 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][17]~COUT
--operation mode is arithmetic

D9L33 = AMPP_FUNCTION(D7_pipe[0][17], D6_pipe[0][19], D9L13);


--Q1_q_b[8] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[8] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[8], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][16] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16]
--operation mode is arithmetic

D9_pipe[0][16] = AMPP_FUNCTION(clk, D7_pipe[0][16], D6_pipe[0][19], VCC, D9L92);

--D9L13 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][16]~COUT
--operation mode is arithmetic

D9L13 = AMPP_FUNCTION(D7_pipe[0][16], D6_pipe[0][19], D9L92);


--Q1_q_b[7] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[7] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[7], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][15] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15]
--operation mode is arithmetic

D9_pipe[0][15] = AMPP_FUNCTION(clk, D7_pipe[0][15], D6_pipe[0][19], VCC, D9L72);

--D9L92 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][15]~COUT
--operation mode is arithmetic

D9L92 = AMPP_FUNCTION(D7_pipe[0][15], D6_pipe[0][19], D9L72);


--Q1_q_b[6] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[6] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[6], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][14] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][14]
--operation mode is arithmetic

D9_pipe[0][14] = AMPP_FUNCTION(clk, D7_pipe[0][14], D6_pipe[0][14], VCC, D9L52);

--D9L72 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][14]~COUT
--operation mode is arithmetic

D9L72 = AMPP_FUNCTION(D7_pipe[0][14], D6_pipe[0][14], D9L52);


--Q1_q_b[5] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[5] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[5], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][13] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][13]
--operation mode is arithmetic

D9_pipe[0][13] = AMPP_FUNCTION(clk, D7_pipe[0][13], D6_pipe[0][13], VCC, D9L32);

--D9L52 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][13]~COUT
--operation mode is arithmetic

D9L52 = AMPP_FUNCTION(D7_pipe[0][13], D6_pipe[0][13], D9L32);


--Q1_q_b[4] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[4] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[4], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][12] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][12]
--operation mode is arithmetic

D9_pipe[0][12] = AMPP_FUNCTION(clk, D7_pipe[0][12], D6_pipe[0][12], VCC, D9L12);

--D9L32 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][12]~COUT
--operation mode is arithmetic

D9L32 = AMPP_FUNCTION(D7_pipe[0][12], D6_pipe[0][12], D9L12);


--Q1_q_b[3] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[3] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[3], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][11] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][11]
--operation mode is arithmetic

D9_pipe[0][11] = AMPP_FUNCTION(clk, D7_pipe[0][11], D6_pipe[0][11], VCC, D9L91);

--D9L12 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][11]~COUT
--operation mode is arithmetic

D9L12 = AMPP_FUNCTION(D7_pipe[0][11], D6_pipe[0][11], D9L91);


--Q1_q_b[2] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[2] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[2], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][10] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][10]
--operation mode is arithmetic

D9_pipe[0][10] = AMPP_FUNCTION(clk, D7_pipe[0][10], D6_pipe[0][10], VCC, D9L71);

--D9L91 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][10]~COUT
--operation mode is arithmetic

D9L91 = AMPP_FUNCTION(D7_pipe[0][10], D6_pipe[0][10], D9L71);


--Q1_q_b[1] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[1] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[1], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][9] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][9]
--operation mode is arithmetic

D9_pipe[0][9] = AMPP_FUNCTION(clk, D7_pipe[0][9], D6_pipe[0][9], VCC, D9L51);

--D9L71 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][9]~COUT
--operation mode is arithmetic

D9L71 = AMPP_FUNCTION(D7_pipe[0][9], D6_pipe[0][9], D9L51);


--Q1_q_b[0] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 11, Port B Logical Depth: 3, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
Q1_q_b[0] = AMPP_FUNCTION(GND, GND, clk, clk, X1_q_b[0], R1_safe_q[0], R1_safe_q[1], N1_dffe3a[0], N1L4);


--D9_pipe[0][8] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][8]
--operation mode is arithmetic

D9_pipe[0][8] = AMPP_FUNCTION(clk, D7_pipe[0][8], D6_pipe[0][8], VCC, D9L31);

--D9L51 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][8]~COUT
--operation mode is arithmetic

D9L51 = AMPP_FUNCTION(D7_pipe[0][8], D6_pipe[0][8], D9L31);


--D9_pipe[0][7] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][7]
--operation mode is arithmetic

D9_pipe[0][7] = AMPP_FUNCTION(clk, D7_pipe[0][7], D6_pipe[0][7], VCC, D9L11);

--D9L31 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][7]~COUT
--operation mode is arithmetic

D9L31 = AMPP_FUNCTION(D7_pipe[0][7], D6_pipe[0][7], D9L11);


--D9_pipe[0][6] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][6]
--operation mode is arithmetic

D9_pipe[0][6] = AMPP_FUNCTION(clk, D7_pipe[0][6], D6_pipe[0][6], VCC, D9L9);

--D9L11 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][6]~COUT
--operation mode is arithmetic

D9L11 = AMPP_FUNCTION(D7_pipe[0][6], D6_pipe[0][6], D9L9);


--D9_pipe[0][5] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][5]
--operation mode is arithmetic

D9_pipe[0][5] = AMPP_FUNCTION(clk, D7_pipe[0][5], D6_pipe[0][5], VCC, D9L7);

--D9L9 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][5]~COUT
--operation mode is arithmetic

D9L9 = AMPP_FUNCTION(D7_pipe[0][5], D6_pipe[0][5], D9L7);


--D9_pipe[0][4] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][4]
--operation mode is arithmetic

D9_pipe[0][4] = AMPP_FUNCTION(clk, D7_pipe[0][4], D6_pipe[0][4], VCC);

--D9L7 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][4]~COUT
--operation mode is arithmetic

D9L7 = AMPP_FUNCTION(D7_pipe[0][4], D6_pipe[0][4]);


--D9_pipe[0][3] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][3]
--operation mode is normal

D9_pipe[0][3] = AMPP_FUNCTION(clk, D6_pipe[0][3], VCC);


--D9_pipe[0][2] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][2]
--operation mode is normal

D9_pipe[0][2] = AMPP_FUNCTION(clk, D6_pipe[0][2], VCC);


--D9_pipe[0][1] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][1]
--operation mode is normal

D9_pipe[0][1] = AMPP_FUNCTION(clk, D6_pipe[0][1], VCC);


--D9_pipe[0][0] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n|pipe[0][0]
--operation mode is normal

D9_pipe[0][0] = AMPP_FUNCTION(clk, D6_pipe[0][0], VCC);


--T1_safe_q[0] is fir321_st:fir321_st_inst|par_ctrl:Uctrl|lpm_counter:cnt_rtl_0|cntr_sv7:auto_generated|safe_q[0]
--operation mode is arithmetic

T1_safe_q[0] = AMPP_FUNCTION(clk, T1_safe_q[0], !rst, E1L1);

--T1L2 is fir321_st:fir321_st_inst|par_ctrl:Uctrl|lpm_counter:cnt_rtl_0|cntr_sv7:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

T1L2 = AMPP_FUNCTION(T1_safe_q[0]);


--T1_safe_q[1] is fir321_st:fir321_st_inst|par_ctrl:Uctrl|lpm_counter:cnt_rtl_0|cntr_sv7:auto_generated|safe_q[1]
--operation mode is arithmetic

T1_safe_q[1] = AMPP_FUNCTION(clk, T1_safe_q[1], !rst, E1L1, T1L2);

--T1L4 is fir321_st:fir321_st_inst|par_ctrl:Uctrl|lpm_counter:cnt_rtl_0|cntr_sv7:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

T1L4 = AMPP_FUNCTION(T1_safe_q[1], T1L2);


--T1_safe_q[2] is fir321_st:fir321_st_inst|par_ctrl:Uctrl|lpm_counter:cnt_rtl_0|cntr_sv7:auto_generated|safe_q[2]
--operation mode is arithmetic

T1_safe_q[2] = AMPP_FUNCTION(clk, T1_safe_q[2], !rst, E1L1, T1L4);

--T1L6 is fir321_st:fir321_st_inst|par_ctrl:Uctrl|lpm_counter:cnt_rtl_0|cntr_sv7:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

T1L6 = AMPP_FUNCTION(T1_safe_q[2], T1L4);


--T1_safe_q[3] is fir321_st:fir321_st_inst|par_ctrl:Uctrl|lpm_counter:cnt_rtl_0|cntr_sv7:auto_generated|safe_q[3]
--operation mode is normal

T1_safe_q[3] = AMPP_FUNCTION(clk, T1_safe_q[3], !rst, E1L1, T1L6);


--E1L1 is fir321_st:fir321_st_inst|par_ctrl:Uctrl|LessThan~47
--operation mode is normal

E1L1 = AMPP_FUNCTION(T1_safe_q[0], T1_safe_q[1], T1_safe_q[2], T1_safe_q[3]);


--X1_q_b[10] is fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 11, Port B Logical Depth: 32, Port B Logical Width: 11
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
X1_q_b[10] = AMPP_FUNCTION(L1_shift_reg[0], GND, coef_in_clk, clk, K1_coef_in_inv[10], J1_cnt_out[0], J1_cnt_out[1], J1_cnt_out[2], J1_cnt_out[3], J1_cnt_out[4], C1_res[8], C2_res[8], C3_res[8], C4_res[8], C5_res[8]);


--R1_safe_q[0] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|cntr_2gc:cntr1|safe_q[0]
--operation mode is arithmetic

R1_safe_q[0] = AMPP_FUNCTION(clk, R1_safe_q[0], ~GND, VCC, R1_modulus_trigger);

--R1L3 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|cntr_2gc:cntr1|counter_cella0~COUT
--operation mode is arithmetic

R1L3 = AMPP_FUNCTION(R1_safe_q[0]);


--R1_safe_q[1] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|cntr_2gc:cntr1|safe_q[1]
--operation mode is arithmetic

R1_safe_q[1] = AMPP_FUNCTION(clk, R1_safe_q[1], ~GND, VCC, R1_modulus_trigger, R1L3);

--R1L5 is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|cntr_2gc:cntr1|counter_cella1~COUT
--operation mode is arithmetic

R1L5 = AMPP_FUNCTION(R1_safe_q[1], R1L3);


--N1_dffe3a[0] is fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|dffe3a[0]
--operation mode is normal

N1_dffe3a[0] = AMPP_FUNCTION(clk, R1_safe_q[0], VCC);