fir321.html
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</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - FIR Compiler MegaCore Function v3.2.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>fir321_st_wr</TD></TR><TR><TD><B>Variation Name</B></TD><TD>fir321</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:\DesignExample\ReloadCoefficient_411_16</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>fir321.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>fir321_inst.v</TD><TD>Verilog HDL sample instantiation file</TD></TR><TR><TD>fir321.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>fir321.inc</TD><TD>An AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>fir321_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>fir321.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>fir321_st.v</TD><TD>Generated FIR Filter Netlist. This file is required for Quartus II synthesis. It will be added to your current Quartus II project.</TD></TR><TR><TD>fir321_st_wr.v</TD><TD>Generated FIR Filter Netlist. This file is required for Quartus II synthesis. It will be added to your current Quartus II project.</TD></TR><TR><TD>fir321_constraints.tcl</TD><TD>Constraints setting file for Quartus II synthesis. This file contains the necessary constraints to achieve FIR Filter size and speed.</TD></TR><TR><TD>fir321_st_s.v</TD><TD>Generated FIR Filter Netlist. This file is required for Quartus II synthesis. It will be added to your current Quartus II project.</TD></TR><TR><TD>fir321_st_u.v</TD><TD>Generated FIR Filter Netlist. This file is required for Quartus II synthesis. It will be added to your current Quartus II project.</TD></TR><TR><TD>fir321_coef_[0..1].hex</TD><TD>Memory initialization files. These files are required both for simulation with IP Functional Simulation Models and for Synthesis using the Quartus II software.</TD></TR><TR><TD>fir321.vo</TD><TD>Verilog HDL IP functional simulation model.</TD></TR><TR><TD>fir321.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rst</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_in</TD><TD>INPUT</TD><TD>16</TD></TR><TR><TD>coef_we</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>coef_in</TD><TD>INPUT</TD><TD>18</TD></TR><TR><TD>coef_in_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>fir_result</TD><TD>OUTPUT</TD><TD>35</TD></TR><TR><TD>done</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rdy_to_ld</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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