fir321.bsf

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

/*
Generated through CNX2HDL Converter version 1.1
*/
/*
Generated by FIR Compiler 3.2.1 [Altera, IP Toolbench v1.2.7 build38]
************************************************************
THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
************************************************************
Copyright (C) 1991-2005 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 230 176)
	(text "fir321" (rect 5 0 30 12)(font "Arial" ))
	(text "inst" (rect 8 144 28 156)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "clk" (rect 0 0 15 12)(font "Arial" ))
		(text "clk" (rect 21 27 36 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "rst" (rect 0 0 15 12)(font "Arial" ))
		(text "rst" (rect 21 43 36 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "data_in[15..0]" (rect 0 0 70 12)(font "Arial" ))
		(text "data_in[15..0]" (rect 21 59 91 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 3))
	)
	(port
		(pt 0 80)
		(input)
		(text "coef_we" (rect 0 0 35 12)(font "Arial" ))
		(text "coef_we" (rect 21 75 56 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "coef_in[17..0]" (rect 0 0 70 12)(font "Arial" ))
		(text "coef_in[17..0]" (rect 21 91 91 103)(font "Arial" ))
		(line (pt 0 96)(pt 16 96)(line_width 3))
	)
	(port
		(pt 0 112)
		(input)
		(text "coef_in_clk" (rect 0 0 55 12)(font "Arial" ))
		(text "coef_in_clk" (rect 21 107 76 119)(font "Arial" ))
		(line (pt 0 112)(pt 16 112)(line_width 1))
	)
	(port
		(pt 214 32)
		(output)
		(text "fir_result[34..0]" (rect 0 0 85 12)(font "Arial" ))
		(text "fir_result[34..0]" (rect 108 27 193 39)(font "Arial" ))
		(line (pt 214 32)(pt 198 32)(line_width 3))
	)
	(port
		(pt 214 48)
		(output)
		(text "done" (rect 0 0 20 12)(font "Arial" ))
		(text "done" (rect 173 43 193 55)(font "Arial" ))
		(line (pt 214 48)(pt 198 48)(line_width 1))
	)
	(port
		(pt 214 64)
		(output)
		(text "rdy_to_ld" (rect 0 0 45 12)(font "Arial" ))
		(text "rdy_to_ld" (rect 148 59 193 71)(font "Arial" ))
		(line (pt 214 64)(pt 198 64)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 198 144)(line_width 1))
	)
)