fir321_silent_param.txt

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

fc_version : 3.2.1
blank_gen : READ
coef_bit_width : 16
coef_conv_sel : AUTO
coef_pow2 : FALSE
data_type : SGN
in_bit_width : 16
num_ch : 16
out_calc_basis : 1
out_full_chk : 1
out_sbf_chk : 0
out_msb_rad : MSB_TRN
out_lsb_rad : LSB_TRN
out_lose_msb : 0
out_lose_lsb : 0
arch_struct_sel : 2
arch_data_store : 0
arch_coef_store : 1
arch_reload_coef : 1
arch_reload_coef_sgl_clock : 0
arch_num_mbs : 4
arch_no_sym : 1
num_bank_set : 1
length : 18
num_cycles : 1
arch_pipeline : 1
poly_type : 1
poly_fact : 4
device_family : 0
use_dsp_block : 0
rate_ctrl : RATE_CTRL_OFF
arch_no_ctrl : 1
m_file_gen : 0
vec_file_gen : 0
vec_clk_per : 10.0