fir321_inst.v

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

// Generated by FIR Compiler 3.2.1 [Altera, IP Toolbench v1.2.7 build38]
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// support information, device programming or simulation file, and any other
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// under Altera's Megafunction Partnership Program may be used only to
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	fir321	fir321_inst(
		.clk(clk_sig),
		.rst(rst_sig),
		.data_in(data_in_sig),
		.coef_we(coef_we_sig),
		.coef_in(coef_in_sig),
		.coef_in_clk(coef_in_clk_sig),
		.fir_result(fir_result_sig),
		.done(done_sig),
		.rdy_to_ld(rdy_to_ld_sig));