fir321.fit.summary

来自「vhdl source,ver-fir-coefficient,simulink」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Fri Mar 11 15:34:18 2005
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : fir321
Top-level Entity Name : fir321
Family : Stratix
Met timing requirements : N/A
Total logic elements : 319 / 10,570 ( 3 % )
Total pins : 45 / 336 ( 13 % )
Total virtual pins : 0
Total memory bits : 3,201 / 920,448 ( < 1 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
Device : EP1S10F484C5
Timing Models : Final