fir321.xml

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

<?xml version="1.0"?>
<MEGACORE title="FIR Compiler MegaCore Function"  version="3.2.1"  iptb_version="v1.2.7 build38"  format_version="120" >
<NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.FIRModelClass"  active_core="fir321_st_wr" >
<STATIC_SECTION>
<PRIVATES>
<NAMESPACE name = "parameterization">
<PRIVATE name = "filter_rate" value="Interpolation"  type="STRING"  enable="1" />
<PRIVATE name = "filter_factor" value="4"  type="INTEGER"  enable="1" />
<PRIVATE name = "coefficient_scaling_type" value="Auto"  type="STRING"  enable="1" />
<PRIVATE name = "coefficient_scaling_factor" value="134521.4368184134"  type="STRING"  enable="0" />
<PRIVATE name = "coefficient_bit_width" value="16"  type="INTEGER"  enable="1" />
<PRIVATE name = "coefficient_binary_point_position" value="0"  type="INTEGER"  enable="0" />
<PRIVATE name = "number_of_input_channels" value="16"  type="INTEGER"  enable="1" />
<PRIVATE name = "input_number_system" value="Signed Binary"  type="STRING"  enable="1" />
<PRIVATE name = "input_bit_width" value="16"  type="INTEGER"  enable="1" />
<PRIVATE name = "input_binary_point_position" value="0"  type="INTEGER"  enable="0" />
<PRIVATE name = "output_bit_width_method" value="Bit Width Only"  type="STRING"  enable="1" />
<PRIVATE name = "output_number_system" value="Full Resolution"  type="STRING"  enable="1" />
<PRIVATE name = "output_bit_width" value="35"  type="INTEGER"  enable="1" />
<PRIVATE name = "output_bits_right_of_binary_point" value="30"  type="INTEGER"  enable="0" />
<PRIVATE name = "output_bits_removed_from_lsb" value="0"  type="INTEGER"  enable="0" />
<PRIVATE name = "output_lsb_remove_type" value="Truncate"  type="STRING"  enable="1" />
<PRIVATE name = "output_msb_remove_type" value="Truncate"  type="STRING"  enable="1" />
<PRIVATE name = "flow_control" value="0"  type="INTEGER"  enable="1" />
<PRIVATE name = "flow_control_input" value="Slave Sink"  type="STRING"  enable="1" />
<PRIVATE name = "flow_control_output" value="Master Source"  type="STRING"  enable="1" />
<PRIVATE name = "device_family" value="Stratix"  type="STRING"  enable="1" />
<PRIVATE name = "structure" value="Distributed Arithmetic : Multi-Bit Serial Filter"  type="STRING"  enable="1" />
<PRIVATE name = "pipeline_level" value="1"  type="INTEGER"  enable="1" />
<PRIVATE name = "clocks_to_compute" value="1"  type="INTEGER"  enable="0" />
<PRIVATE name = "number_of_serial_units" value="4"  type="INTEGER"  enable="1" />
<PRIVATE name = "data_storage" value="Logic Cells"  type="STRING"  enable="1" />
<PRIVATE name = "coefficient_storage" value="M512"  type="STRING"  enable="1" />
<PRIVATE name = "multiplier_storage" value="Logic Cells"  type="STRING"  enable="0" />
<PRIVATE name = "force_non_symmetric_structure" value="1"  type="BOOLEAN"  enable="0" />
<PRIVATE name = "coefficients_reload" value="1"  type="BOOLEAN"  enable="1" />
<PRIVATE name = "coefficients_reload_sgl_clock" value="0"  type="BOOLEAN"  enable="1" />
<PRIVATE name = "max_clocks_to_compute" value="4"  type="INTEGER"  enable="1" />
<PRIVATE name = "set_1" value="Low Pass Set, Floating, Low Pass, Rectangular, 18, 1.0E7, 1250000.0, 3750000.0, 0, 0.0143276, -0.0162381, -0.0452338, -0.0534586, -0.0270641, 0.0347973, 0.117612, 0.19602, 0.243582, 0.243582, 0.19602, 0.117612, 0.0347973, -0.0270641, -0.0534586, -0.0452338, -0.0162381, 0.0143276"  type="STRING"  enable="1" />
<PRIVATE name = "number_of_sets" value="1"  type="INTEGER"  enable="1" />
<PRIVATE name = "output_full_bit_width" value="35"  type="INTEGER"  enable="1" />
<PRIVATE name = "output_full_bits_right_of_binary_point" value="30"  type="INTEGER"  enable="1" />
<PRIVATE name = "logic_cell" value="5620"  type="INTEGER"  enable="1" />
<PRIVATE name = "m512" value="8"  type="INTEGER"  enable="1" />
<PRIVATE name = "m4k" value="0"  type="INTEGER"  enable="1" />
<PRIVATE name = "megaram" value="0"  type="INTEGER"  enable="1" />
<PRIVATE name = "dsp_block" value="0"  type="INTEGER"  enable="1" />
<PRIVATE name = "input_clock_period" value="16"  type="INTEGER"  enable="1" />
<PRIVATE name = "output_clock_period" value="4"  type="INTEGER"  enable="1" />
<PRIVATE name = "throughput" value="4"  type="INTEGER"  enable="1" />
<PRIVATE name = "memory_units" value="2"  type="INTEGER"  enable="1" />
</NAMESPACE>
<NAMESPACE name = "simgen_enable">
<PRIVATE name = "matlab_enable" value="0"  type="BOOLEAN"  enable="1" />
<PRIVATE name = "testbench_enable" value="0"  type="BOOLEAN"  enable="1" />
<PRIVATE name = "testbench_simulation_clock_period" value="10.0"  type="STRING"  enable="1" />
<PRIVATE name = "language" value="Verilog HDL"  type="STRING"  enable="1" />
<PRIVATE name = "enabled" value="1"  type="BOOLEAN"  enable="1" />
</NAMESPACE>
<NAMESPACE name = "symbol"/>
<NAMESPACE name = "quartus_settings">
<PRIVATE name = "DEVICE" value="AUTO"  type="STRING"  enable="1" />
<PRIVATE name = "FAMILY" value="Stratix"  type="STRING"  enable="1" />
</NAMESPACE>
<NAMESPACE name = "serializer"/>
</PRIVATES>
<FILES/>
<PORTS/>
<LIBRARIES/>
</STATIC_SECTION>
</NETLIST_SECTION>
</MEGACORE>