fir321.map.rpt

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

; Total 0-input functions           ; 2       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 310     ;
; Total logic cells in carry chains ; 171     ;
; I/O pins                          ; 45      ;
; Total memory bits                 ; 3201    ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 391     ;
; Total fan-out                     ; 2609    ;
; Average fan-out                   ; 5.49    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                             ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+-----------------------+
; Name                                                                                                                                                    ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                   ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+-----------------------+
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_1_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_2_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_4_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_5_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_6_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_7_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0.hex     ;
; fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|ALTSYNCRAM               ; M512 ; Simple Dual Port ; 32           ; 11           ; 32           ; 11           ; 352  ; fir321_coef_0_inv.hex ;
; fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|altshift_taps:pipe_rtl_1|shift_taps_3lg:auto_generated|altsyncram_b5q:altsyncram4|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 3            ; 11           ; 3            ; 11           ; 33   ; None                  ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+-----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Fri Mar 11 15:33:51 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fir321 -c fir321
Info: Found 1 design units, including 1 entities, in source file fir321.v
    Info: Found entity 1: fir321
Info: Found 1 design units, including 1 entities, in source file fir321_st.v
    Info: Found entity 1: fir321_st
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/tdl_da_lc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: tdl_da_lc
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/coef_in_conv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: coef_in_conv
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/addr_cnt_up.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: addr_cnt_up
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/ser_shift.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ser_shift
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/sadd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sadd
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/ram_lut.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ram_lut
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/ram_2pt_var_cen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ram_2pt_var_cen
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus42/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1jf1.tdf
    Info: Found entity 1: altsyncram_1jf1
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_d0g1.tdf
    Info: Found entity 1: altsyncram_d0g1
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/sadd_lpm_cen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sadd_lpm_cen
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/mac_tl.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: mac_tl
Info: Using design file ../../../../MegaCore/fir_compiler-v3.2.1/lib/par_ctrl.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: par_ctrl
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n|pipe[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n|pipe[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n|pipe[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][6]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][5]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n|pipe[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][5]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n|pipe[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n|pipe[0][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n|pipe[0][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n|pipe[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n|pipe[0][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_2_n_1_n|pipe[0][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n|pipe[0][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n|pipe[0][6]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n|pipe[0][5]" with stuck data_in port to stuck value GND
Warning: Reduced register "fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n|pipe[0][4]" with stuck data_in port to stuck value GND
Warning: Re