at91sam9263.inc

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· INC 代码 · 共 920 行 · 第 1/5 页

AT91C_CKGR_DIVA           EQU (0xFF:SHL:0) ;- (CKGR) Divider A Selected
AT91C_CKGR_DIVA_0         EQU (0x0) ;- (CKGR) Divider A output is 0
AT91C_CKGR_DIVA_BYPASS    EQU (0x1) ;- (CKGR) Divider A is bypassed
AT91C_CKGR_PLLACOUNT      EQU (0x3F:SHL:8) ;- (CKGR) PLL A Counter
AT91C_CKGR_OUTA           EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency Range
AT91C_CKGR_OUTA_0         EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
AT91C_CKGR_OUTA_1         EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
AT91C_CKGR_OUTA_2         EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
AT91C_CKGR_OUTA_3         EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
AT91C_CKGR_MULA           EQU (0x7FF:SHL:16) ;- (CKGR) PLL A Multiplier
AT91C_CKGR_SRCA           EQU (0x1:SHL:29) ;- (CKGR) 
;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
AT91C_CKGR_DIVB           EQU (0xFF:SHL:0) ;- (CKGR) Divider B Selected
AT91C_CKGR_DIVB_0         EQU (0x0) ;- (CKGR) Divider B output is 0
AT91C_CKGR_DIVB_BYPASS    EQU (0x1) ;- (CKGR) Divider B is bypassed
AT91C_CKGR_PLLBCOUNT      EQU (0x3F:SHL:8) ;- (CKGR) PLL B Counter
AT91C_CKGR_OUTB           EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency Range
AT91C_CKGR_OUTB_0         EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
AT91C_CKGR_OUTB_1         EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
AT91C_CKGR_OUTB_2         EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
AT91C_CKGR_OUTB_3         EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
AT91C_CKGR_MULB           EQU (0x7FF:SHL:16) ;- (CKGR) PLL B Multiplier
AT91C_CKGR_USBDIV         EQU (0x3:SHL:28) ;- (CKGR) Divider for USB Clocks
AT91C_CKGR_USBDIV_0       EQU (0x0:SHL:28) ;- (CKGR) Divider output is PLL clock output
AT91C_CKGR_USBDIV_1       EQU (0x1:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 2
AT91C_CKGR_USBDIV_2       EQU (0x2:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 4

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Power Management Controler
;- *****************************************************************************
                ^ 0 ;- AT91S_PMC
PMC_SCER        #  4 ;- System Clock Enable Register
PMC_SCDR        #  4 ;- System Clock Disable Register
PMC_SCSR        #  4 ;- System Clock Status Register
                #  4 ;- Reserved
PMC_PCER        #  4 ;- Peripheral Clock Enable Register
PMC_PCDR        #  4 ;- Peripheral Clock Disable Register
PMC_PCSR        #  4 ;- Peripheral Clock Status Register
                #  4 ;- Reserved
PMC_MOR         #  4 ;- Main Oscillator Register
PMC_MCFR        #  4 ;- Main Clock  Frequency Register
PMC_PLLAR       #  4 ;- PLL A Register
PMC_PLLBR       #  4 ;- PLL B Register
PMC_MCKR        #  4 ;- Master Clock Register
                # 12 ;- Reserved
PMC_PCKR        # 32 ;- Programmable Clock Register
PMC_IER         #  4 ;- Interrupt Enable Register
PMC_IDR         #  4 ;- Interrupt Disable Register
PMC_SR          #  4 ;- Status Register
PMC_IMR         #  4 ;- Interrupt Mask Register
;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
AT91C_PMC_PCK             EQU (0x1:SHL:0) ;- (PMC) Processor Clock
AT91C_PMC_OTG             EQU (0x1:SHL:5) ;- (PMC) USB OTG Clock
AT91C_PMC_UHP             EQU (0x1:SHL:6) ;- (PMC) USB Host Port Clock
AT91C_PMC_UDP             EQU (0x1:SHL:7) ;- (PMC) USB Device Port Clock
AT91C_PMC_PCK0            EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK1            EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK2            EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK3            EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output
;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
;- -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
;- -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
;- -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- 
;- -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- 
;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
AT91C_PMC_CSS             EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection
AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
AT91C_PMC_CSS_PLLA_CLK    EQU (0x2) ;- (PMC) Clock from PLL A is selected
AT91C_PMC_CSS_PLLB_CLK    EQU (0x3) ;- (PMC) Clock from PLL B is selected
AT91C_PMC_PRES            EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler
AT91C_PMC_PRES_CLK        EQU (0x0:SHL:2) ;- (PMC) Selected clock
AT91C_PMC_PRES_CLK_2      EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2
AT91C_PMC_PRES_CLK_4      EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4
AT91C_PMC_PRES_CLK_8      EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8
AT91C_PMC_PRES_CLK_16     EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16
AT91C_PMC_PRES_CLK_32     EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32
AT91C_PMC_PRES_CLK_64     EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64
AT91C_PMC_MDIV            EQU (0x3:SHL:8) ;- (PMC) Master Clock Division
AT91C_PMC_MDIV_1          EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the same
AT91C_PMC_MDIV_2          EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clock
AT91C_PMC_MDIV_3          EQU (0x2:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock
;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
AT91C_PMC_MOSCS           EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask
AT91C_PMC_LOCKA           EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/Mask
AT91C_PMC_LOCKB           EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/Mask
AT91C_PMC_MCKRDY          EQU (0x1:SHL:3) ;- (PMC) Master Clock Status/Enable/Disable/Mask
AT91C_PMC_PCK0RDY         EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK1RDY         EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK2RDY         EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK3RDY         EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Reset Controller Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_RSTC
RSTC_RCR        #  4 ;- Reset Control Register
RSTC_RSR        #  4 ;- Reset Status Register
RSTC_RMR        #  4 ;- Reset Mode Register
;- -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
AT91C_RSTC_PROCRST        EQU (0x1:SHL:0) ;- (RSTC) Processor Reset
AT91C_RSTC_ICERST         EQU (0x1:SHL:1) ;- (RSTC) ICE Interface Reset
AT91C_RSTC_PERRST         EQU (0x1:SHL:2) ;- (RSTC) Peripheral Reset
AT91C_RSTC_EXTRST         EQU (0x1:SHL:3) ;- (RSTC) External Reset
AT91C_RSTC_KEY            EQU (0xFF:SHL:24) ;- (RSTC) Password
;- -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
AT91C_RSTC_URSTS          EQU (0x1:SHL:0) ;- (RSTC) User Reset Status
AT91C_RSTC_RSTTYP         EQU (0x7:SHL:8) ;- (RSTC) Reset Type
AT91C_RSTC_RSTTYP_GENERAL EQU (0x0:SHL:8) ;- (RSTC) General reset. Both VDDCORE and VDDBU rising.
AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1:SHL:8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2:SHL:8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3:SHL:8) ;- (RSTC) Software Reset. Processor reset required by the software.
AT91C_RSTC_RSTTYP_USER    EQU (0x4:SHL:8) ;- (RSTC) User Reset. NRST pin detected low.
AT91C_RSTC_NRSTL          EQU (0x1:SHL:16) ;- (RSTC) NRST pin level
AT91C_RSTC_SRCMP          EQU (0x1:SHL:17) ;- (RSTC) Software Reset Command in Progress.
;- -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
AT91C_RSTC_URSTEN         EQU (0x1:SHL:0) ;- (RSTC) User Reset Enable
AT91C_RSTC_URSTIEN        EQU (0x1:SHL:4) ;- (RSTC) User Reset Interrupt Enable
AT91C_RSTC_ERSTL          EQU (0xF:SHL:8) ;- (RSTC) User Reset Enable

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_SHDWC
SHDWC_SHCR      #  4 ;- Shut Down Control Register
SHDWC_SHMR      #  4 ;- Shut Down Mode Register
SHDWC_SHSR      #  4 ;- Shut Down Status Register
;- -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- 
AT91C_SHDWC_SHDW          EQU (0x1:SHL:0) ;- (SHDWC) Processor Reset
AT91C_SHDWC_KEY           EQU (0xFF:SHL:24) ;- (SHDWC) Shut down KEY Password
;- -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- 
AT91C_SHDWC_WKMODE0       EQU (0x3:SHL:0) ;- (SHDWC) Wake Up 0 Mode Selection
AT91C_SHDWC_WKMODE0_NONE  EQU (0x0) ;- (SHDWC) None. No detection is performed on the wake up input.
AT91C_SHDWC_WKMODE0_HIGH  EQU (0x1) ;- (SHDWC) High Level.
AT91C_SHDWC_WKMODE0_LOW   EQU (0x2) ;- (SHDWC) Low Level.
AT91C_SHDWC_WKMODE0_ANYLEVEL EQU (0x3) ;- (SHDWC) Any level change.
AT91C_SHDWC_CPTWK0        EQU (0xF:SHL:4) ;- (SHDWC) Counter On Wake Up 0
AT91C_SHDWC_RTTWKEN       EQU (0x1:SHL:16) ;- (SHDWC) Real Time Timer Wake Up Enable
;- -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- 
AT91C_SHDWC_WAKEUP0       EQU (0x1:SHL:0) ;- (SHDWC) Wake Up 0 Status
AT91C_SHDWC_RTTWK         EQU (0x1:SHL:16) ;- (SHDWC) Real Time Timer wake Up

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_RTTC
RTTC_RTMR       #  4 ;- Real-time Mode Register
RTTC_RTAR       #  4 ;- Real-time Alarm Register
RTTC_RTVR       #  4 ;- Real-time Value Register
RTTC_RTSR       #  4 ;- Real-time Status Register
;- -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
AT91C_RTTC_RTPRES         EQU (0xFFFF:SHL:0) ;- (RTTC) Real-time Timer Prescaler Value
AT91C_RTTC_ALMIEN         EQU (0x1:SHL:16) ;- (RTTC) Alarm Interrupt Enable
AT91C_RTTC_RTTINCIEN      EQU (0x1:SHL:17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
AT91C_RTTC_RTTRST         EQU (0x1:SHL:18) ;- (RTTC) Real Time Timer Restart
;- -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
AT91C_RTTC_ALMV           EQU (0x0:SHL:0) ;- (RTTC) Alarm Value
;- -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
AT91C_RTTC_CRTV           EQU (0x0:SHL:0) ;- (RTTC) Current Real-time Value
;- -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
AT91C_RTTC_ALMS           EQU (0x1:SHL:0) ;- (RTTC) Real-time Alarm Status
AT91C_RTTC_RTTINC         EQU (0x1:SHL:1) ;- (RTTC) Real-time Timer Increment

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_PITC
PITC_PIMR       #  4 ;- Period Interval Mode Register
PITC_PISR       #  4 ;- Period Interval Status Register
PITC_PIVR       #  4 ;- Period Interval Value Register
PITC_PIIR       #  4 ;- Period Interval Image Register
;- -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
AT91C_PITC_PIV            EQU (0xFFFFF:SHL:0) ;- (PITC) Periodic Interval Value
AT91C_PITC_PITEN          EQU (0x1:SHL:24) ;- (PITC) Periodic Interval Timer Enabled
AT91C_PITC_PITIEN         EQU (0x1:SHL:25) ;- (PITC) Periodic Interval Timer Interrupt Enable
;- -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
AT91C_PITC_PITS           EQU (0x1:SHL:0) ;- (PITC) Periodic Interval Timer Status
;- -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
AT91C_PITC_CPIV           EQU (0xFFFFF:SHL:0)