at91sam9263.inc

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· INC 代码 · 共 920 行 · 第 1/5 页

MATRIX_SCFG7    #  4 ;-  Slave Configuration Register 7
                # 32 ;- Reserved
MATRIX_PRAS0    #  4 ;-  PRAS0
MATRIX_PRBS0    #  4 ;-  PRBS0
MATRIX_PRAS1    #  4 ;-  PRAS1
MATRIX_PRBS1    #  4 ;-  PRBS1
MATRIX_PRAS2    #  4 ;-  PRAS2
MATRIX_PRBS2    #  4 ;-  PRBS2
MATRIX_PRAS3    #  4 ;-  PRAS3
MATRIX_PRBS3    #  4 ;-  PRBS3
MATRIX_PRAS4    #  4 ;-  PRAS4
MATRIX_PRBS4    #  4 ;-  PRBS4
MATRIX_PRAS5    #  4 ;-  PRAS5
MATRIX_PRBS5    #  4 ;-  PRBS5
MATRIX_PRAS6    #  4 ;-  PRAS6
MATRIX_PRBS6    #  4 ;-  PRBS6
MATRIX_PRAS7    #  4 ;-  PRAS7
MATRIX_PRBS7    #  4 ;-  PRBS7
                # 64 ;- Reserved
MATRIX_MRCR     #  4 ;-  Master Remp Control Register 
;- -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register rom -------- 
AT91C_MATRIX_ULBT         EQU (0x7:SHL:0) ;- (MATRIX) Undefined Length Burst Type
;- -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register htcm -------- 
;- -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register gps_tcm -------- 
;- -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register hperiphs -------- 
;- -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register ebi0 -------- 
;- -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register ebi1 -------- 
;- -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register bridge -------- 
;- -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register gps -------- 
;- -------- MATRIX_MCFG8 : (MATRIX Offset: 0x20) Master Configuration Register gps -------- 
;- -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- 
AT91C_MATRIX_SLOT_CYCLE   EQU (0xFF:SHL:0) ;- (MATRIX) Maximum Number of Allowed Cycles for a Burst
AT91C_MATRIX_DEFMSTR_TYPE EQU (0x3:SHL:16) ;- (MATRIX) Default Master Type
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR EQU (0x0:SHL:16) ;- (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR EQU (0x1:SHL:16) ;- (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR EQU (0x2:SHL:16) ;- (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
AT91C_MATRIX_FIXED_DEFMSTR0 EQU (0x7:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_PDC EQU (0x2:SHL:18) ;- (MATRIX) PDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_2DGC EQU (0x4:SHL:18) ;- (MATRIX) 2DGC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_ISI EQU (0x5:SHL:18) ;- (MATRIX) ISI Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_EMAC EQU (0x7:SHL:18) ;- (MATRIX) EMAC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_USB EQU (0x8:SHL:18) ;- (MATRIX) USB Master is Default Master
AT91C_MATRIX_ARBT         EQU (0x3:SHL:24) ;- (MATRIX) Arbitration Type
;- -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- 
AT91C_MATRIX_FIXED_DEFMSTR1 EQU (0x7:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_PDC EQU (0x2:SHL:18) ;- (MATRIX) PDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_2DGC EQU (0x4:SHL:18) ;- (MATRIX) 2DGC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_ISI EQU (0x5:SHL:18) ;- (MATRIX) ISI Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_EMAC EQU (0x7:SHL:18) ;- (MATRIX) EMAC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_USB EQU (0x8:SHL:18) ;- (MATRIX) USB Master is Default Master
;- -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- 
AT91C_MATRIX_FIXED_DEFMSTR2 EQU (0x1:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR2_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
;- -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- 
AT91C_MATRIX_FIXED_DEFMSTR3 EQU (0x7:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_PDC EQU (0x2:SHL:18) ;- (MATRIX) PDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_2DGC EQU (0x4:SHL:18) ;- (MATRIX) 2DGC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_ISI EQU (0x5:SHL:18) ;- (MATRIX) ISI Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_EMAC EQU (0x7:SHL:18) ;- (MATRIX) EMAC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_USB EQU (0x8:SHL:18) ;- (MATRIX) USB Master is Default Master
;- -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- 
AT91C_MATRIX_FIXED_DEFMSTR4 EQU (0x3:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR4_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
;- -------- MATRIX_SCFG5 : (MATRIX Offset: 0x54) Slave Configuration Register 5 -------- 
AT91C_MATRIX_FIXED_DEFMSTR5 EQU (0x3:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_PDC EQU (0x2:SHL:18) ;- (MATRIX) PDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_2DGC EQU (0x4:SHL:18) ;- (MATRIX) 2DGC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_ISI EQU (0x5:SHL:18) ;- (MATRIX) ISI Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_EMAC EQU (0x7:SHL:18) ;- (MATRIX) EMAC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR5_USB EQU (0x8:SHL:18) ;- (MATRIX) USB Master is Default Master
;- -------- MATRIX_SCFG6 : (MATRIX Offset: 0x58) Slave Configuration Register 6 -------- 
AT91C_MATRIX_FIXED_DEFMSTR6 EQU (0x3:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_PDC EQU (0x2:SHL:18) ;- (MATRIX) PDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_2DGC EQU (0x4:SHL:18) ;- (MATRIX) 2DGC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_ISI EQU (0x5:SHL:18) ;- (MATRIX) ISI Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_EMAC EQU (0x7:SHL:18) ;- (MATRIX) EMAC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR6_USB EQU (0x8:SHL:18) ;- (MATRIX) USB Master is Default Master
;- -------- MATRIX_SCFG7 : (MATRIX Offset: 0x5c) Slave Configuration Register 7 -------- 
AT91C_MATRIX_FIXED_DEFMSTR7 EQU (0x3:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR7_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR7_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR7_PDC EQU (0x2:SHL:18) ;- (MATRIX) PDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR7_DMA EQU (0x6:SHL:18) ;- (MATRIX) DMA Controller Master is Default Master
;- -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- 
AT91C_MATRIX_M0PR         EQU (0x3:SHL:0) ;- (MATRIX) ARM926EJ-S Instruction priority
AT91C_MATRIX_M1PR         EQU (0x3:SHL:4) ;- (MATRIX) ARM926EJ-S Data priority
AT91C_MATRIX_M2PR         EQU (0x3:SHL:8) ;- (MATRIX) PDC priority
AT91C_MATRIX_M3PR         EQU (0x3:SHL:12) ;- (MATRIX) LCDC priority
AT91C_MATRIX_M4PR         EQU (0x3:SHL:16) ;- (MATRIX) 2DGC priority
AT91C_MATRIX_M5PR         EQU (0x3:SHL:20) ;- (MATRIX) ISI priority
AT91C_MATRIX_M6PR         EQU (0x3:SHL:24) ;- (MATRIX) DMA priority
AT91C_MATRIX_M7PR         EQU (0x3:SHL:28) ;- (MATRIX) EMAC priority
;- -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- 
AT91C_MATRIX_M8PR         EQU (0x3:SHL:0) ;- (MATRIX) USB priority
;- -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- 
;- -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- 
;- -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- 
;- -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- 
;- -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- 
;- -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- 
;- -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- 
;- -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- 
;- -------- MATRIX_PRAS5 : (MATRIX Offset: 0xa8) PRAS5 Register -------- 
;- -------- MATRIX_PRBS5 : (MATRIX Offset: 0xac) PRBS5 Register -------- 
;- -------- MATRIX_PRAS6 : (MATRIX Offset: 0xb0) PRAS6 Register -------- 
;- -------- MATRIX_PRBS6 : (MATRIX Offset: 0xb4) PRBS6 Register -------- 
;- -------- MATRIX_PRAS7 : (MATRIX Offset: 0xb8) PRAS7 Register -------- 
;- -------- MATRIX_PRBS7 : (MATRIX Offset: 0xbc) PRBS7 Register -------- 
;- -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- 
AT91C_MATRIX_RCA926I      EQU (0x1:SHL:0) ;- (MATRIX) Remap Command Bit for ARM926EJ-S Instruction
AT91C_MATRIX_RCA926D      EQU (0x1:SHL:1) ;- (MATRIX) Remap Command Bit for ARM926EJ-S Data
AT91C_MATRIX_RCB2         EQU (0x1:SHL:2) ;- (MATRIX) Remap Command Bit for PDC
AT91C_MATRIX_RCB3         EQU (0x1:SHL:3) ;- (MATRIX) Remap Command Bit for LCD
AT91C_MATRIX_RCB4         EQU (0x1:SHL:4) ;- (MATRIX) Remap Command Bit for 2DGC
AT91C_MATRIX_RCB5         EQU (0x1:SHL:5) ;- (MATRIX) Remap Command Bit for ISI
AT91C_MATRIX_RCB6         EQU (0x1:SHL:6) ;- (MATRIX) Remap Command Bit for DMA
AT91C_MATRIX_RCB7         EQU (0x1:SHL:7) ;- (MATRIX) Remap Command Bit for EMAC
AT91C_MATRIX_RCB8         EQU (0x1:SHL:8) ;- (MATRIX) Remap Command Bit for USB

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR AHB CCFG Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_CCFG
                #  4 ;- Reserved
CCFG_TCMR       #  4 ;-  TCM configuration
                #  8 ;- Reserved
CCFG_EBI0CSA    #  4 ;-  EBI0 Chip Select Assignement Register
CCFG_EBI1CSA    #  4 ;-  EBI1 Chip Select Assignement Register
                # 212 ;- Reserved
CCFG_MATRIXVERSION #  4 ;-  Version Register
;- -------- CCFG_TCMR : (CCFG Offset: 0x4) TCM Configuration -------- 
AT91C_CCFG_ITCM_SIZE      EQU (0xF:SHL:0) ;- (CCFG) Size of ITCM enabled memory block
AT91C_CCFG_ITCM_SIZE_0KB  EQU (0x0) ;- (CCFG) 0 KB (No ITCM Memory)
AT91C_CCFG_ITCM_SIZE_16KB EQU (0x5) ;- (CCFG) 16 KB
AT91C_CCFG_ITCM_SIZE_32KB EQU (0x6) ;- (CCFG) 32 KB
AT91C_CCFG_DTCM_SIZE      EQU (0xF:SHL:4) ;- (CCFG) Size of DTCM enabled memory block
AT91C_CCFG_DTCM_SIZE_0KB  EQU (0x0:SHL:4) ;- (CCFG) 0 KB (No DTCM Memory)
AT91C_CCFG_DTCM_SIZE_16KB EQU (0x5:SHL:4) ;- (CCFG) 16 KB
AT91C_CCFG_DTCM_SIZE_32KB EQU (0x6:SHL:4) ;- (CCFG) 32 KB
AT91C_CCFG_RM             EQU (0xF:SHL:8) ;- (CCFG) Read Margin registers
;- -------- CCFG_EBI0CSA : (CCFG Offset: 0x10) EBI0 Chip Select Assignment Register -------- 
AT91C_EBI_CS1A            EQU (0x1:SHL:1) ;- (CCFG) Chip Select 1 Assignment
AT91C_EBI_CS1A_SMC        EQU (0x0:SHL:1) ;- (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
AT91C_EBI_CS1A_SDRAMC     EQU (0x1:SHL:1) ;- (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
AT91C_EBI_CS3A            EQU (0x1:SHL:3) ;- (CCFG) Chip Select 3 Assignment
AT91C_EBI_CS3A_SMC        EQU (0x0:SHL:3) ;- (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
AT91C_EBI_CS3A_SM         EQU (0x1:SHL:3) ;- (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
AT91C_EBI_CS4A            EQU (0x1:SHL:4) ;- (CCFG) Chip Select 4 Assignment
AT91C_EBI_CS4A_SMC        EQU (0x0:SHL:4) ;- (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
AT91C_EBI_CS4A_CF         EQU (0x1:SHL:4) ;- (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
AT91C_EBI_CS5A            EQU (0x1:SHL:5) ;- (CCFG) Chip Select 5 Assignment
AT91C_EBI_CS5A_SMC        EQU (0x0:SHL:5) ;- (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
AT91C_EBI_CS5A_CF         EQU (0x1:SHL:5) ;- (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
AT91C_EBI_DBPUC           EQU (0x1:SHL:8) ;- (CCFG) Data Bus Pull-up Configuration
;- -------- CCFG_EBI1CSA : (CCFG Offset: 0x14) EBI1 Chip Select Assignement Register -------- 
AT91C_EBI_CS2A            EQU (0x1:SHL:3) ;- (CCFG) EBI1 Chip Select 2 Assignment
AT91C_EBI_CS2A_SMC        EQU (0x0:SHL:3) ;- (CCFG) Chip Select 2 is assigned to the Static Memory Controller.
AT91C_EBI_CS2A_SM         EQU (0x1:SHL:3) ;- (CCFG) Chip Select 2 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.

;- *****************************************************************************