at91sam9263.tcl
来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· TCL 代码 · 共 1,152 行 · 第 1/5 页
TCL
1,152 行
set AT91C_MATRIX_M1PR [expr 0x3 << 4 ]
set AT91C_MATRIX_M2PR [expr 0x3 << 8 ]
set AT91C_MATRIX_M3PR [expr 0x3 << 12 ]
set AT91C_MATRIX_M4PR [expr 0x3 << 16 ]
set AT91C_MATRIX_M5PR [expr 0x3 << 20 ]
set AT91C_MATRIX_M6PR [expr 0x3 << 24 ]
set AT91C_MATRIX_M7PR [expr 0x3 << 28 ]
# -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register --------
set AT91C_MATRIX_M8PR [expr 0x3 << 0 ]
# -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register --------
set AT91C_MATRIX_M0PR [expr 0x3 << 0 ]
set AT91C_MATRIX_M1PR [expr 0x3 << 4 ]
set AT91C_MATRIX_M2PR [expr 0x3 << 8 ]
set AT91C_MATRIX_M3PR [expr 0x3 << 12 ]
set AT91C_MATRIX_M4PR [expr 0x3 << 16 ]
set AT91C_MATRIX_M5PR [expr 0x3 << 20 ]
set AT91C_MATRIX_M6PR [expr 0x3 << 24 ]
set AT91C_MATRIX_M7PR [expr 0x3 << 28 ]
# -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register --------
set AT91C_MATRIX_M8PR [expr 0x3 << 0 ]
# -------- MATRIX_PRAS5 : (MATRIX Offset: 0xa8) PRAS5 Register --------
set AT91C_MATRIX_M0PR [expr 0x3 << 0 ]
set AT91C_MATRIX_M1PR [expr 0x3 << 4 ]
set AT91C_MATRIX_M2PR [expr 0x3 << 8 ]
set AT91C_MATRIX_M3PR [expr 0x3 << 12 ]
set AT91C_MATRIX_M4PR [expr 0x3 << 16 ]
set AT91C_MATRIX_M5PR [expr 0x3 << 20 ]
set AT91C_MATRIX_M6PR [expr 0x3 << 24 ]
set AT91C_MATRIX_M7PR [expr 0x3 << 28 ]
# -------- MATRIX_PRBS5 : (MATRIX Offset: 0xac) PRBS5 Register --------
set AT91C_MATRIX_M8PR [expr 0x3 << 0 ]
# -------- MATRIX_PRAS6 : (MATRIX Offset: 0xb0) PRAS6 Register --------
set AT91C_MATRIX_M0PR [expr 0x3 << 0 ]
set AT91C_MATRIX_M1PR [expr 0x3 << 4 ]
set AT91C_MATRIX_M2PR [expr 0x3 << 8 ]
set AT91C_MATRIX_M3PR [expr 0x3 << 12 ]
set AT91C_MATRIX_M4PR [expr 0x3 << 16 ]
set AT91C_MATRIX_M5PR [expr 0x3 << 20 ]
set AT91C_MATRIX_M6PR [expr 0x3 << 24 ]
set AT91C_MATRIX_M7PR [expr 0x3 << 28 ]
# -------- MATRIX_PRBS6 : (MATRIX Offset: 0xb4) PRBS6 Register --------
set AT91C_MATRIX_M8PR [expr 0x3 << 0 ]
# -------- MATRIX_PRAS7 : (MATRIX Offset: 0xb8) PRAS7 Register --------
set AT91C_MATRIX_M0PR [expr 0x3 << 0 ]
set AT91C_MATRIX_M1PR [expr 0x3 << 4 ]
set AT91C_MATRIX_M2PR [expr 0x3 << 8 ]
set AT91C_MATRIX_M3PR [expr 0x3 << 12 ]
set AT91C_MATRIX_M4PR [expr 0x3 << 16 ]
set AT91C_MATRIX_M5PR [expr 0x3 << 20 ]
set AT91C_MATRIX_M6PR [expr 0x3 << 24 ]
set AT91C_MATRIX_M7PR [expr 0x3 << 28 ]
# -------- MATRIX_PRBS7 : (MATRIX Offset: 0xbc) PRBS7 Register --------
set AT91C_MATRIX_M8PR [expr 0x3 << 0 ]
# -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
set AT91C_MATRIX_RCA926I [expr 0x1 << 0 ]
set AT91C_MATRIX_RCA926D [expr 0x1 << 1 ]
set AT91C_MATRIX_RCB2 [expr 0x1 << 2 ]
set AT91C_MATRIX_RCB3 [expr 0x1 << 3 ]
set AT91C_MATRIX_RCB4 [expr 0x1 << 4 ]
set AT91C_MATRIX_RCB5 [expr 0x1 << 5 ]
set AT91C_MATRIX_RCB6 [expr 0x1 << 6 ]
set AT91C_MATRIX_RCB7 [expr 0x1 << 7 ]
set AT91C_MATRIX_RCB8 [expr 0x1 << 8 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR AHB CCFG Interface
# *****************************************************************************
# -------- CCFG_TCMR : (CCFG Offset: 0x4) TCM Configuration --------
set AT91C_CCFG_ITCM_SIZE [expr 0xF << 0 ]
set AT91C_CCFG_ITCM_SIZE_0KB 0x0
set AT91C_CCFG_ITCM_SIZE_16KB 0x5
set AT91C_CCFG_ITCM_SIZE_32KB 0x6
set AT91C_CCFG_DTCM_SIZE [expr 0xF << 4 ]
set AT91C_CCFG_DTCM_SIZE_0KB [expr 0x0 << 4 ]
set AT91C_CCFG_DTCM_SIZE_16KB [expr 0x5 << 4 ]
set AT91C_CCFG_DTCM_SIZE_32KB [expr 0x6 << 4 ]
set AT91C_CCFG_RM [expr 0xF << 8 ]
# -------- CCFG_EBI0CSA : (CCFG Offset: 0x10) EBI0 Chip Select Assignment Register --------
set AT91C_EBI_CS1A [expr 0x1 << 1 ]
set AT91C_EBI_CS1A_SMC [expr 0x0 << 1 ]
set AT91C_EBI_CS1A_SDRAMC [expr 0x1 << 1 ]
set AT91C_EBI_CS3A [expr 0x1 << 3 ]
set AT91C_EBI_CS3A_SMC [expr 0x0 << 3 ]
set AT91C_EBI_CS3A_SM [expr 0x1 << 3 ]
set AT91C_EBI_CS4A [expr 0x1 << 4 ]
set AT91C_EBI_CS4A_SMC [expr 0x0 << 4 ]
set AT91C_EBI_CS4A_CF [expr 0x1 << 4 ]
set AT91C_EBI_CS5A [expr 0x1 << 5 ]
set AT91C_EBI_CS5A_SMC [expr 0x0 << 5 ]
set AT91C_EBI_CS5A_CF [expr 0x1 << 5 ]
set AT91C_EBI_DBPUC [expr 0x1 << 8 ]
# -------- CCFG_EBI1CSA : (CCFG Offset: 0x14) EBI1 Chip Select Assignement Register --------
set AT91C_EBI_CS1A [expr 0x1 << 1 ]
set AT91C_EBI_CS1A_SMC [expr 0x0 << 1 ]
set AT91C_EBI_CS1A_SDRAMC [expr 0x1 << 1 ]
set AT91C_EBI_CS2A [expr 0x1 << 3 ]
set AT91C_EBI_CS2A_SMC [expr 0x0 << 3 ]
set AT91C_EBI_CS2A_SM [expr 0x1 << 3 ]
set AT91C_EBI_DBPUC [expr 0x1 << 8 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Peripheral DMA Controller
# *****************************************************************************
# -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
set AT91C_PDC_RXTEN [expr 0x1 << 0 ]
set AT91C_PDC_RXTDIS [expr 0x1 << 1 ]
set AT91C_PDC_TXTEN [expr 0x1 << 8 ]
set AT91C_PDC_TXTDIS [expr 0x1 << 9 ]
# -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
set AT91C_PDC_RXTEN [expr 0x1 << 0 ]
set AT91C_PDC_TXTEN [expr 0x1 << 8 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Debug Unit
# *****************************************************************************
# -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
set AT91C_US_RSTRX [expr 0x1 << 2 ]
set AT91C_US_RSTTX [expr 0x1 << 3 ]
set AT91C_US_RXEN [expr 0x1 << 4 ]
set AT91C_US_RXDIS [expr 0x1 << 5 ]
set AT91C_US_TXEN [expr 0x1 << 6 ]
set AT91C_US_TXDIS [expr 0x1 << 7 ]
set AT91C_US_RSTSTA [expr 0x1 << 8 ]
# -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
set AT91C_US_PAR [expr 0x7 << 9 ]
set AT91C_US_PAR_EVEN [expr 0x0 << 9 ]
set AT91C_US_PAR_ODD [expr 0x1 << 9 ]
set AT91C_US_PAR_SPACE [expr 0x2 << 9 ]
set AT91C_US_PAR_MARK [expr 0x3 << 9 ]
set AT91C_US_PAR_NONE [expr 0x4 << 9 ]
set AT91C_US_PAR_MULTI_DROP [expr 0x6 << 9 ]
set AT91C_US_CHMODE [expr 0x3 << 14 ]
set AT91C_US_CHMODE_NORMAL [expr 0x0 << 14 ]
set AT91C_US_CHMODE_AUTO [expr 0x1 << 14 ]
set AT91C_US_CHMODE_LOCAL [expr 0x2 << 14 ]
set AT91C_US_CHMODE_REMOTE [expr 0x3 << 14 ]
# -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
set AT91C_US_FORCE_NTRST [expr 0x1 << 0 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
# *****************************************************************************
# -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
set AT91C_AIC_PRIOR [expr 0x7 << 0 ]
set AT91C_AIC_PRIOR_LOWEST 0x0
set AT91C_AIC_PRIOR_HIGHEST 0x7
set AT91C_AIC_SRCTYPE [expr 0x3 << 5 ]
set AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE [expr 0x0 << 5 ]
set AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED [expr 0x1 << 5 ]
set AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL [expr 0x2 << 5 ]
set AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE [expr 0x3 << 5 ]
# -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
set AT91C_AIC_NFIQ [expr 0x1 << 0 ]
set AT91C_AIC_NIRQ [expr 0x1 << 1 ]
# -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
set AT91C_AIC_DCR_PROT [expr 0x1 << 0 ]
set AT91C_AIC_DCR_GMSK [expr 0x1 << 1 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Parallel Input Output Controler
# *****************************************************************************
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Clock Generator Controler
# *****************************************************************************
# -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
set AT91C_CKGR_MOSCEN [expr 0x1 << 0 ]
set AT91C_CKGR_OSCBYPASS [expr 0x1 << 1 ]
set AT91C_CKGR_OSCOUNT [expr 0xFF << 8 ]
# -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
set AT91C_CKGR_MAINF [expr 0xFFFF << 0 ]
set AT91C_CKGR_MAINRDY [expr 0x1 << 16 ]
# -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
set AT91C_CKGR_DIVA [expr 0xFF << 0 ]
set AT91C_CKGR_DIVA_0 0x0
set AT91C_CKGR_DIVA_BYPASS 0x1
set AT91C_CKGR_PLLACOUNT [expr 0x3F << 8 ]
set AT91C_CKGR_OUTA [expr 0x3 << 14 ]
set AT91C_CKGR_OUTA_0 [expr 0x0 << 14 ]
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