at91sam9263.tcl
来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· TCL 代码 · 共 1,152 行 · 第 1/5 页
TCL
1,152 行
# ----------------------------------------------------------------------------
# ATMEL Microcontroller Software Support - ROUSSET -
# ----------------------------------------------------------------------------
# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# ----------------------------------------------------------------------------
# File Name : AT91SAM9263.tcl
# Object : AT91SAM9263 definitions
# Generated : AT91 SW Application Group 12/07/2006 (13:13:45)
#
# CVS Reference : /AT91SAM9263.pl/1.2/Fri Nov 10 12:56:00 2006//
# CVS Reference : /SYS_SAM9262.pl/1.4/Tue Jan 18 17:06:33 2005//
# CVS Reference : /HMATRIX1_SAM9262.pl/1.10/Thu Oct 13 12:44:26 2005//
# CVS Reference : /CCR_SAM9262.pl/1.7/Fri Nov 10 13:23:00 2006//
# CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//
# CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
# CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
# CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
# CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
# CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
# CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
# CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
# CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004//
# CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
# CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
# CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
# CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
# CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005//
# CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006//
# CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
# CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
# CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
# CVS Reference : /AC97C_XXXX.pl/1.3/Tue Feb 22 17:08:27 2005//
# CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
# CVS Reference : /PWM_6044D.pl/1.2/Tue May 10 12:39:09 2005//
# CVS Reference : /LCDC_6063A.pl/1.3/Fri Dec 9 10:59:26 2005//
# CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
# CVS Reference : /DMA_XXXX.pl/1.6/Tue Jan 11 09:40:44 2005//
# CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
# CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
# CVS Reference : /TBOX_XXXX.pl/1.15/Thu Jun 9 07:05:57 2005//
# CVS Reference : /EBI_nadia2.pl/1.1/Wed Dec 29 11:28:03 2004//
# CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//
# CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005//
# ----------------------------------------------------------------------------
# *****************************************************************************
# SOFTWARE API DEFINITION FOR System Peripherals
# *****************************************************************************
# -------- GPBR : (SYS Offset: 0x1d60) GPBR General Purpose Register --------
set AT91C_GPBR_GPRV [expr 0x0 << 0 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR External Bus Interface 0
# *****************************************************************************
# *****************************************************************************
# SOFTWARE API DEFINITION FOR SDRAM Controller Interface
# *****************************************************************************
# -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
set AT91C_SDRAMC_MODE [expr 0xF << 0 ]
set AT91C_SDRAMC_MODE_NORMAL_CMD 0x0
set AT91C_SDRAMC_MODE_NOP_CMD 0x1
set AT91C_SDRAMC_MODE_PRCGALL_CMD 0x2
set AT91C_SDRAMC_MODE_LMR_CMD 0x3
set AT91C_SDRAMC_MODE_RFSH_CMD 0x4
set AT91C_SDRAMC_MODE_EXT_LMR_CMD 0x5
set AT91C_SDRAMC_MODE_DEEP_CMD 0x6
# -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
set AT91C_SDRAMC_COUNT [expr 0xFFF << 0 ]
# -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
set AT91C_SDRAMC_NC [expr 0x3 << 0 ]
set AT91C_SDRAMC_NC_8 0x0
set AT91C_SDRAMC_NC_9 0x1
set AT91C_SDRAMC_NC_10 0x2
set AT91C_SDRAMC_NC_11 0x3
set AT91C_SDRAMC_NR [expr 0x3 << 2 ]
set AT91C_SDRAMC_NR_11 [expr 0x0 << 2 ]
set AT91C_SDRAMC_NR_12 [expr 0x1 << 2 ]
set AT91C_SDRAMC_NR_13 [expr 0x2 << 2 ]
set AT91C_SDRAMC_NB [expr 0x1 << 4 ]
set AT91C_SDRAMC_NB_2_BANKS [expr 0x0 << 4 ]
set AT91C_SDRAMC_NB_4_BANKS [expr 0x1 << 4 ]
set AT91C_SDRAMC_CAS [expr 0x3 << 5 ]
set AT91C_SDRAMC_CAS_2 [expr 0x2 << 5 ]
set AT91C_SDRAMC_CAS_3 [expr 0x3 << 5 ]
set AT91C_SDRAMC_DBW [expr 0x1 << 7 ]
set AT91C_SDRAMC_DBW_32_BITS [expr 0x0 << 7 ]
set AT91C_SDRAMC_DBW_16_BITS [expr 0x1 << 7 ]
set AT91C_SDRAMC_TWR [expr 0xF << 8 ]
set AT91C_SDRAMC_TWR_0 [expr 0x0 << 8 ]
set AT91C_SDRAMC_TWR_1 [expr 0x1 << 8 ]
set AT91C_SDRAMC_TWR_2 [expr 0x2 << 8 ]
set AT91C_SDRAMC_TWR_3 [expr 0x3 << 8 ]
set AT91C_SDRAMC_TWR_4 [expr 0x4 << 8 ]
set AT91C_SDRAMC_TWR_5 [expr 0x5 << 8 ]
set AT91C_SDRAMC_TWR_6 [expr 0x6 << 8 ]
set AT91C_SDRAMC_TWR_7 [expr 0x7 << 8 ]
set AT91C_SDRAMC_TWR_8 [expr 0x8 << 8 ]
set AT91C_SDRAMC_TWR_9 [expr 0x9 << 8 ]
set AT91C_SDRAMC_TWR_10 [expr 0xA << 8 ]
set AT91C_SDRAMC_TWR_11 [expr 0xB << 8 ]
set AT91C_SDRAMC_TWR_12 [expr 0xC << 8 ]
set AT91C_SDRAMC_TWR_13 [expr 0xD << 8 ]
set AT91C_SDRAMC_TWR_14 [expr 0xE << 8 ]
set AT91C_SDRAMC_TWR_15 [expr 0xF << 8 ]
set AT91C_SDRAMC_TRC [expr 0xF << 12 ]
set AT91C_SDRAMC_TRC_0 [expr 0x0 << 12 ]
set AT91C_SDRAMC_TRC_1 [expr 0x1 << 12 ]
set AT91C_SDRAMC_TRC_2 [expr 0x2 << 12 ]
set AT91C_SDRAMC_TRC_3 [expr 0x3 << 12 ]
set AT91C_SDRAMC_TRC_4 [expr 0x4 << 12 ]
set AT91C_SDRAMC_TRC_5 [expr 0x5 << 12 ]
set AT91C_SDRAMC_TRC_6 [expr 0x6 << 12 ]
set AT91C_SDRAMC_TRC_7 [expr 0x7 << 12 ]
set AT91C_SDRAMC_TRC_8 [expr 0x8 << 12 ]
set AT91C_SDRAMC_TRC_9 [expr 0x9 << 12 ]
set AT91C_SDRAMC_TRC_10 [expr 0xA << 12 ]
set AT91C_SDRAMC_TRC_11 [expr 0xB << 12 ]
set AT91C_SDRAMC_TRC_12 [expr 0xC << 12 ]
set AT91C_SDRAMC_TRC_13 [expr 0xD << 12 ]
set AT91C_SDRAMC_TRC_14 [expr 0xE << 12 ]
set AT91C_SDRAMC_TRC_15 [expr 0xF << 12 ]
set AT91C_SDRAMC_TRP [expr 0xF << 16 ]
set AT91C_SDRAMC_TRP_0 [expr 0x0 << 16 ]
set AT91C_SDRAMC_TRP_1 [expr 0x1 << 16 ]
set AT91C_SDRAMC_TRP_2 [expr 0x2 << 16 ]
set AT91C_SDRAMC_TRP_3 [expr 0x3 << 16 ]
set AT91C_SDRAMC_TRP_4 [expr 0x4 << 16 ]
set AT91C_SDRAMC_TRP_5 [expr 0x5 << 16 ]
set AT91C_SDRAMC_TRP_6 [expr 0x6 << 16 ]
set AT91C_SDRAMC_TRP_7 [expr 0x7 << 16 ]
set AT91C_SDRAMC_TRP_8 [expr 0x8 << 16 ]
set AT91C_SDRAMC_TRP_9 [expr 0x9 << 16 ]
set AT91C_SDRAMC_TRP_10 [expr 0xA << 16 ]
set AT91C_SDRAMC_TRP_11 [expr 0xB << 16 ]
set AT91C_SDRAMC_TRP_12 [expr 0xC << 16 ]
set AT91C_SDRAMC_TRP_13 [expr 0xD << 16 ]
set AT91C_SDRAMC_TRP_14 [expr 0xE << 16 ]
set AT91C_SDRAMC_TRP_15 [expr 0xF << 16 ]
set AT91C_SDRAMC_TRCD [expr 0xF << 20 ]
set AT91C_SDRAMC_TRCD_0 [expr 0x0 << 20 ]
set AT91C_SDRAMC_TRCD_1 [expr 0x1 << 20 ]
set AT91C_SDRAMC_TRCD_2 [expr 0x2 << 20 ]
set AT91C_SDRAMC_TRCD_3 [expr 0x3 << 20 ]
set AT91C_SDRAMC_TRCD_4 [expr 0x4 << 20 ]
set AT91C_SDRAMC_TRCD_5 [expr 0x5 << 20 ]
set AT91C_SDRAMC_TRCD_6 [expr 0x6 << 20 ]
set AT91C_SDRAMC_TRCD_7 [expr 0x7 << 20 ]
set AT91C_SDRAMC_TRCD_8 [expr 0x8 << 20 ]
set AT91C_SDRAMC_TRCD_9 [expr 0x9 << 20 ]
set AT91C_SDRAMC_TRCD_10 [expr 0xA << 20 ]
set AT91C_SDRAMC_TRCD_11 [expr 0xB << 20 ]
set AT91C_SDRAMC_TRCD_12 [expr 0xC << 20 ]
set AT91C_SDRAMC_TRCD_13 [expr 0xD << 20 ]
set AT91C_SDRAMC_TRCD_14 [expr 0xE << 20 ]
set AT91C_SDRAMC_TRCD_15 [expr 0xF << 20 ]
set AT91C_SDRAMC_TRAS [expr 0xF << 24 ]
set AT91C_SDRAMC_TRAS_0 [expr 0x0 << 24 ]
set AT91C_SDRAMC_TRAS_1 [expr 0x1 << 24 ]
set AT91C_SDRAMC_TRAS_2 [expr 0x2 << 24 ]
set AT91C_SDRAMC_TRAS_3 [expr 0x3 << 24 ]
set AT91C_SDRAMC_TRAS_4 [expr 0x4 << 24 ]
set AT91C_SDRAMC_TRAS_5 [expr 0x5 << 24 ]
set AT91C_SDRAMC_TRAS_6 [expr 0x6 << 24 ]
set AT91C_SDRAMC_TRAS_7 [expr 0x7 << 24 ]
set AT91C_SDRAMC_TRAS_8 [expr 0x8 << 24 ]
set AT91C_SDRAMC_TRAS_9 [expr 0x9 << 24 ]
set AT91C_SDRAMC_TRAS_10 [expr 0xA << 24 ]
set AT91C_SDRAMC_TRAS_11 [expr 0xB << 24 ]
set AT91C_SDRAMC_TRAS_12 [expr 0xC << 24 ]
set AT91C_SDRAMC_TRAS_13 [expr 0xD << 24 ]
set AT91C_SDRAMC_TRAS_14 [expr 0xE << 24 ]
set AT91C_SDRAMC_TRAS_15 [expr 0xF << 24 ]
set AT91C_SDRAMC_TXSR [expr 0xF << 28 ]
set AT91C_SDRAMC_TXSR_0 [expr 0x0 << 28 ]
set AT91C_SDRAMC_TXSR_1 [expr 0x1 << 28 ]
set AT91C_SDRAMC_TXSR_2 [expr 0x2 << 28 ]
set AT91C_SDRAMC_TXSR_3 [expr 0x3 << 28 ]
set AT91C_SDRAMC_TXSR_4 [expr 0x4 << 28 ]
set AT91C_SDRAMC_TXSR_5 [expr 0x5 << 28 ]
set AT91C_SDRAMC_TXSR_6 [expr 0x6 << 28 ]
set AT91C_SDRAMC_TXSR_7 [expr 0x7 << 28 ]
set AT91C_SDRAMC_TXSR_8 [expr 0x8 << 28 ]
set AT91C_SDRAMC_TXSR_9 [expr 0x9 << 28 ]
set AT91C_SDRAMC_TXSR_10 [expr 0xA << 28 ]
set AT91C_SDRAMC_TXSR_11 [expr 0xB << 28 ]
set AT91C_SDRAMC_TXSR_12 [expr 0xC << 28 ]
set AT91C_SDRAMC_TXSR_13 [expr 0xD << 28 ]
set AT91C_SDRAMC_TXSR_14 [expr 0xE << 28 ]
set AT91C_SDRAMC_TXSR_15 [expr 0xF << 28 ]
# -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
set AT91C_SDRAMC_DA [expr 0x1 << 0 ]
set AT91C_SDRAMC_DA_DISABLE 0x0
set AT91C_SDRAMC_DA_ENABLE 0x1
# -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
set AT91C_SDRAMC_LPCB [expr 0x3 << 0 ]
set AT91C_SDRAMC_LPCB_DISABLE 0x0
set AT91C_SDRAMC_LPCB_SELF_REFRESH 0x1
set AT91C_SDRAMC_LPCB_POWER_DOWN 0x2
set AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN 0x3
set AT91C_SDRAMC_PASR [expr 0x7 << 4 ]
set AT91C_SDRAMC_TCSR [expr 0x3 << 8 ]
set AT91C_SDRAMC_DS [expr 0x3 << 10 ]
set AT91C_SDRAMC_TIMEOUT [expr 0x3 << 12 ]
set AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr 0x0 << 12 ]
set AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr 0x1 << 12 ]
set AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr 0x2 << 12 ]
# -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
set AT91C_SDRAMC_MD [expr 0x3 << 0 ]
set AT91C_SDRAMC_MD_SDRAM 0x0
set AT91C_SDRAMC_MD_LOW_POWER_SDRAM 0x1
# *****************************************************************************
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