fft.csf.qmsg

关于FFT实现的Verilog代码

{  "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 29 21:22:50 2006 " "Info: Processing started: Sun Oct 29 21:22:50 2006" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off fft -c fft " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off fft -c fft" {  } {  } 0 }
{  "Info" "IMPP_MPP_USER_DEVICE" "fft EP1S10B672C6 " "Info: Selected device EP1S10B672C6 for design fft" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may compatible with other devices. " { { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S20B672C6 " "Info: Device EP1S20B672C6 is compatible" {  } {  } 2} { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S25B672C6 " "Info: Device EP1S25B672C6 is compatible" {  } {  } 2}  } {  } 2 }
{  "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in Pin R26 " "Info: Automatically promoted signal clk to use Global clock in Pin R26" {  } { { "e:\\whj\\fft.v" "" "" { Text "e:\\whj\\fft.v" 3 -1 0 } }  } 0 }
{  "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 }
{  "Info" "ITAN_NO_USER_LONG_PATH_CONSTRAINTS_FOUND" "" "Info: No timing requirements specified -- optimizing all clocks equally to maximize operation frequency" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_START_REG_LOCATION_PROCESSING" "" "Info: Packing registers due to location constraints" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_FINISH_REG_LOCATION_PROCESSING" "" "Info: Finished packing registers due to location constraints" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP Scan-chain Inferencing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0 }