fft.tan.qmsg

关于FFT实现的Verilog代码

{  "Info" "ITDB_FULL_TPD_RESULT" "x1_im\[6\] out2_im1\[6\] 6.518 ns Shortest " "Info: Shortest tpd from source pin x1_im\[6\] to destination pin out2_im1\[6\] is 6.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns x1_im\[6\] 1 PIN Pin_C10 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_C10; PIN Node = 'x1_im\[6\]'" {  } { { "e:\\whj\\db\\fft_cmp.qrpt" "" "" { Report "e:\\whj\\db\\fft_cmp.qrpt" Compiler "fft" "UNKNOWN" "V1" "e:\\whj\\db\\fft.quartus_db" { Floorplan "" "" "" { x1_im[6] } "NODE_NAME" } } } { "e:\\whj\\fft.v" "" "" { Text "e:\\whj\\fft.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.306 ns) + CELL(0.332 ns) 2.614 ns lpm_add_sua:add_x1_x2_im1\|lpm_add_sub:lpm_add_sub_component\|alt_stratix_add_sub:stratix_adder\|result\[6\] 2 COMB LC_X12_Y30_N6 " "Info: 2: + IC(1.306 ns) + CELL(0.332 ns) = 2.614 ns; Loc. = LC_X12_Y30_N6; COMB Node = 'lpm_add_sua:add_x1_x2_im1\|lpm_add_sub:lpm_add_sub_component\|alt_stratix_add_sub:stratix_adder\|result\[6\]'" {  } { { "e:\\whj\\db\\fft_cmp.qrpt" "" "" { Report "e:\\whj\\db\\fft_cmp.qrpt" Compiler "fft" "UNKNOWN" "V1" "e:\\whj\\db\\fft.quartus_db" { Floorplan "" "" "1.638 ns" { x1_im[6] lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6] } "NODE_NAME" } } } { "d:\\program files\\ww\\libraries\\megafunctions\\alt_stratix_add_sub.tdf" "" "" { Text "d:\\program files\\ww\\libraries\\megafunctions\\alt_stratix_add_sub.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.404 ns) + CELL(2.500 ns) 6.518 ns out2_im1\[6\] 3 PIN Pin_E3 " "Info: 3: + IC(1.404 ns) + CELL(2.500 ns) = 6.518 ns; Loc. = Pin_E3; PIN Node = 'out2_im1\[6\]'" {  } { { "e:\\whj\\db\\fft_cmp.qrpt" "" "" { Report "e:\\whj\\db\\fft_cmp.qrpt" Compiler "fft" "UNKNOWN" "V1" "e:\\whj\\db\\fft.quartus_db" { Floorplan "" "" "3.904 ns" { lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6] out2_im1[6] } "NODE_NAME" } } } { "e:\\whj\\fft.v" "" "" { Text "e:\\whj\\fft.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.808 ns " "Info: Total cell delay = 3.808 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.710 ns " "Info: Total interconnect delay = 2.710 ns" {  } {  } 0}  } { { "e:\\whj\\db\\fft_cmp.qrpt" "" "" { Report "e:\\whj\\db\\fft_cmp.qrpt" Compiler "fft" "UNKNOWN" "V1" "e:\\whj\\db\\fft.quartus_db" { Floorplan "" "" "6.518 ns" { x1_im[6] x1_im[6]~out0 lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6] out2_im1[6] } "NODE_NAME" } } }  } 0 }
{  "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 29 21:23:48 2006 " "Info: Processing ended: Sun Oct 29 21:23:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0 }
{  "Info" "IQCU_REPORT_WRITTEN_TO" "fft.tan.rpt " "Info: Writing report file fft.tan.rpt" {  } {  } 0 }