fft.tan.qmsg

关于FFT实现的Verilog代码

{  "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 29 21:23:47 2006 " "Info: Processing started: Sun Oct 29 21:23:47 2006" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off fft -c fft --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off fft -c fft --timing_analysis_only" {  } {  } 0 }
{  "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "e:\\whj\\fft.v" "" "" { Text "e:\\whj\\fft.v" 3 -1 0 } } { "d:\\program files\\ww\\bin\\Assignment Editor.qase" "" "" { Assignment "d:\\program files\\ww\\bin\\Assignment Editor.qase" 1 { { { 0 "clk" } } } } }  } 0}  } {  } 0 }
{  "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register paths exist for clock clk" {  } {  } 0 }