fft.fit.qmsg

来自「关于FFT实现的Verilog代码」· QMSG 代码 · 共 29 行

{  "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 29 21:22:50 2006 " "Info: Processing started: Sun Oct 29 21:22:50 2006" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off fft -c fft " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off fft -c fft" {  } {  } 0 }
{  "Info" "IMPP_MPP_USER_DEVICE" "fft EP1S10B672C6 " "Info: Selected device EP1S10B672C6 for design fft" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may compatible with other devices. " { { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S20B672C6 " "Info: Device EP1S20B672C6 is compatible" {  } {  } 2} { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S25B672C6 " "Info: Device EP1S25B672C6 is compatible" {  } {  } 2}  } {  } 2 }
{  "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in Pin R26 " "Info: Automatically promoted signal clk to use Global clock in Pin R26" {  } { { "e:\\whj\\fft.v" "" "" { Text "e:\\whj\\fft.v" 3 -1 0 } }  } 0 }
{  "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 }
{  "Info" "ITAN_NO_USER_LONG_PATH_CONSTRAINTS_FOUND" "" "Info: No timing requirements specified -- optimizing all clocks equally to maximize operation frequency" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_START_REG_LOCATION_PROCESSING" "" "Info: Packing registers due to location constraints" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_FINISH_REG_LOCATION_PROCESSING" "" "Info: Finished packing registers due to location constraints" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP Scan-chain Inferencing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF " "Info: Statistics of I/O pins that use the same VCCIO and VREF" { { "Info" "IFYGR_FYGR_SINGLE_IOC_GROUP_STATISTICS" "209 unused 3.30 49 160 0 " "Info: There are 209 I/O pins (VREF = unused, VCCIO = 3.30, 49 input, 160 output, 0 bidirectional)" { { "Info" "IFYGR_FYGR_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: Used I/O standards LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0 }
{  "Info" "IFYGR_FYGR_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O banks and pin(s) statistics before I/O pin placement" { { "Info" "IFYGR_FYGR_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "1 unused unused 0 39 " "Info: I/O bank 1: VREF = unused, VCCIO = unused, used pin 0, available pins 39." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "2 unused unused 0 39 " "Info: I/O bank 2: VREF = unused, VCCIO = unused, used pin 0, available pins 39." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "3 unused unused 0 43 " "Info: I/O bank 3: VREF = unused, VCCIO = unused, used pin 0, available pins 43." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "4 unused unused 1 44 " "Info: I/O bank 4: VREF = unused, VCCIO = unused, used pin 1, available pins 44." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "5 unused unused 0 39 " "Info: I/O bank 5: VREF = unused, VCCIO = unused, used pin 0, available pins 39." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "6 unused unused 1 38 " "Info: I/O bank 6: VREF = unused, VCCIO = unused, used pin 1, available pins 38." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "7 unused unused 0 45 " "Info: I/O bank 7: VREF = unused, VCCIO = unused, used pin 0, available pins 45." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "8 unused unused 0 44 " "Info: I/O bank 8: VREF = unused, VCCIO = unused, used pin 0, available pins 44." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "9 unused unused 0 6 " "Info: I/O bank 9: VREF = unused, VCCIO = unused, used pin 0, available pins 6." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "10 unused unused 0 0 " "Info: I/O bank 10: VREF = unused, VCCIO = unused, used pin 0, available pins 0." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "11 unused unused 0 6 " "Info: I/O bank 11: VREF = unused, VCCIO = unused, used pin 0, available pins 6." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "12 unused unused 0 0 " "Info: I/O bank 12: VREF = unused, VCCIO = unused, used pin 0, available pins 0." {  } {  } 0}  } {  } 0}  } {  } 0 }
{  "Info" "IFYGR_FYGR_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: I/O banks and pin(s) statistics after I/O pin placement" { { "Info" "IFYGR_FYGR_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "1 unused unused 39 0 " "Info: I/O bank 1: VREF = unused, VCCIO = unused, used pin 39, available pins 0." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "2 unused unused 10 29 " "Info: I/O bank 2: VREF = unused, VCCIO = unused, used pin 10, available pins 29." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "3 unused unused 0 43 " "Info: I/O bank 3: VREF = unused, VCCIO = unused, used pin 0, available pins 43." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "4 unused unused 1 44 " "Info: I/O bank 4: VREF = unused, VCCIO = unused, used pin 1, available pins 44." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "5 unused 3.30 36 3 " "Info: I/O bank 5: VREF = unused, VCCIO = 3.30, used pin 36, available pins 3." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "6 unused 3.30 37 2 " "Info: I/O bank 6: VREF = unused, VCCIO = 3.30, used pin 37, available pins 2." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "7 unused 3.30 43 2 " "Info: I/O bank 7: VREF = unused, VCCIO = 3.30, used pin 43, available pins 2." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "8 unused 3.30 42 2 " "Info: I/O bank 8: VREF = unused, VCCIO = 3.30, used pin 42, available pins 2." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "9 unused 3.30 3 3 " "Info: I/O bank 9: VREF = unused, VCCIO = 3.30, used pin 3, available pins 3." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "10 unused unused 0 0 " "Info: I/O bank 10: VREF = unused, VCCIO = unused, used pin 0, available pins 0." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "11 unused unused 0 6 " "Info: I/O bank 11: VREF = unused, VCCIO = unused, used pin 0, available pins 6." {  } {  } 0} { "Info" "IFYGR_FYGR_SINGLE_IO_BANK_STATISTICS" "12 unused unused 0 0 " "Info: I/O bank 12: VREF = unused, VCCIO = unused, used pin 0, available pins 0." {  } {  } 0}  } {  } 0}  } {  } 0 }
{  "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "I/O Pin Placement Operation " "Info: Completed I/O Pin Placement Operation" {  } {  } 0 }
{  "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 }
{  "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 29 21:23:41 2006 " "Info: Processing ended: Sun Oct 29 21:23:41 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:51 " "Info: Elapsed time: 00:00:51" {  } {  } 0}  } {  } 0 }
{  "Info" "IQCU_REPORT_WRITTEN_TO" "fft.fit.rpt " "Info: Writing report file fft.fit.rpt" {  } {  } 0 }