fft.map.qmsg

关于FFT实现的Verilog代码

{  "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 29 21:22:46 2006 " "Info: Processing started: Sun Oct 29 21:22:46 2006" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off fft -c fft " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fft -c fft" {  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:\\whj\\fft.v 1 1 " "Info: Found 1 design units and 1 entities in source file e:\\whj\\fft.v" { { "Info" "ISGN_ENTITY_NAME" "1 fft " "Info: Found entity 1: fft" {  } { { "e:\\whj\\fft.v" "fft" "" { Text "e:\\whj\\fft.v" 1 -1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:\\whj\\lpm_mula.v 1 1 " "Info: Found 1 design units and 1 entities in source file e:\\whj\\lpm_mula.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mula " "Info: Found entity 1: lpm_mula" {  } { { "e:\\whj\\lpm_mula.v" "lpm_mula" "" { Text "e:\\whj\\lpm_mula.v" 37 -1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:\\program files\\ww\\libraries\\megafunctions\\lpm_mult.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file d:\\program files\\ww\\libraries\\megafunctions\\lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "d:\\program files\\ww\\libraries\\megafunctions\\lpm_mult.tdf" "lpm_mult" "" { Text "d:\\program files\\ww\\libraries\\megafunctions\\lpm_mult.tdf" 277 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:\\whj\\db\\mult_6bk.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:\\whj\\db\\mult_6bk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_6bk " "Info: Found entity 1: mult_6bk" {  } { { "e:\\whj\\db\\mult_6bk.tdf" "mult_6bk" "" { Text "e:\\whj\\db\\mult_6bk.tdf" 34 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:\\whj\\lpm_add_sub_16.v 1 1 " "Info: Found 1 design units and 1 entities in source file e:\\whj\\lpm_add_sub_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub_16 " "Info: Found entity 1: lpm_add_sub_16" {  } { { "e:\\whj\\lpm_add_sub_16.v" "lpm_add_sub_16" "" { Text "e:\\whj\\lpm_add_sub_16.v" 37 -1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:\\program files\\ww\\libraries\\megafunctions\\lpm_add_sub.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file d:\\program files\\ww\\libraries\\megafunctions\\lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "d:\\program files\\ww\\libraries\\megafunctions\\lpm_add_sub.tdf" "lpm_add_sub" "" { Text "d:\\program files\\ww\\libraries\\megafunctions\\lpm_add_sub.tdf" 97 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:\\program files\\ww\\libraries\\megafunctions\\alt_stratix_add_sub.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file d:\\program files\\ww\\libraries\\megafunctions\\alt_stratix_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_stratix_add_sub " "Info: Found entity 1: alt_stratix_add_sub" {  } { { "d:\\program files\\ww\\libraries\\megafunctions\\alt_stratix_add_sub.tdf" "alt_stratix_add_sub" "" { Text "d:\\program files\\ww\\libraries\\megafunctions\\alt_stratix_add_sub.tdf" 98 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:\\whj\\lpm_add_sua.v 1 1 " "Info: Found 1 design units and 1 entities in source file e:\\whj\\lpm_add_sua.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sua " "Info: Found entity 1: lpm_add_sua" {  } { { "e:\\whj\\lpm_add_sua.v" "lpm_add_sua" "" { Text "e:\\whj\\lpm_add_sua.v" 37 -1 0 } }  } 0}  } {  } 0 }
{  "Info" "IRTL_INFERENCING_SUMMARY" "0 " "Info: Inferred 0 megafunctions from design logic" {  } {  } 0 }
{  "Info" "ISCL_SCL_TM_SUMMARY" "310 " "Info: Implemented 310 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "50 " "Info: Implemented 50 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "160 " "Info: Implemented 160 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "96 " "Info: Implemented 96 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "4 " "Info: Implemented 4 DSP elements" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 29 21:22:48 2006 " "Info: Processing ended: Sun Oct 29 21:22:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0 }
{  "Info" "IQCU_REPORT_WRITTEN_TO" "fft.map.rpt " "Info: Writing report file fft.map.rpt" {  } {  } 0 }