fft.v

关于FFT实现的Verilog代码

module fft(start,clk,x2_re,x2_im,x1_re,x1_im,w_re,w_im,out2_re,out2_im,out1_re,out1_im);
input [7:0]x2_re,x2_im,x1_re,x1_im,W_RE,W_IM;
output [7:0]out2_re,out2_im,out1_re,out1_im;
reg [7:0]out2_re,out2_im,out1_re,out1_im,out_x2_w;
reg [15:0]out1,ou2,out3,out4;
reg t;
reg [15:0]out_re,out_im;


always@(posedge clk)
if(start==1)
begin 
	
	lpm_mula mult_x2_w_re(x2_re,w_re,out1);
	lpm_mula mult_x2_w_im(x2_im,w_im,out2);
	lpm_mula mult_x2_w_re_im(x2_re,w_im,out3);
	lpm_mula mult_x2_w_im_re(x2_im,w_re,out4);
	lpm_add_sua out1_out2(start,out1,out2,out_re);
	lpm_add_sua out3_out4(start,out3,out4,out_im);
	t<=1;
	if(t)begin
	lpm_add_sua add_x1_x2_re(start,x1_re,out_re[13:6],out1_re);
	lpm_add_sua add_x1_x2_re(start,x1_re,out_re[13:6],out1_re);	
	lpm_add_sua add_x1_x2_im(start,x1_im,out_im[13:6],out1_im);
	lpm_add_sua add_x1_x2_im(!start,x1_im,out_im[13:6],out2_im);
end
endmodule