fft.fit.rpt

来自「关于FFT实现的Verilog代码」· RPT 代码 · 共 394 行 · 第 1/5 页

; DSP block 9-bit elements ; 4 / 48 ( 8 % )                        ;
; Total PLLs               ; 0 / 6 ( 0 % )                         ;
; Total DLLs               ; 0 / 2 ( 0 % )                         ;
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; Flow Settings                               ;
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; Option                ; Setting             ;
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; Start date & time     ; 10/29/2006 21:22:46 ;
; Main task             ; Compilation         ;
; Compiler Setting Name ; fft                 ;
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; Flow Elapsed Time                   ;
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; Module Name          ; Elapsed Time ;
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; Analysis & Synthesis ; 00:00:02     ;
; Fitter               ; 00:00:51     ;
; Total                ; 00:00:53     ;
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; Fitter Summary                                                   ;
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; Fitter Status            ; Successful - Sun Oct 29 21:23:41 2006 ;
; Compiler Setting Name    ; fft                                   ;
; Top-level Entity Name    ; fft                                   ;
; Family                   ; Stratix                               ;
; Device                   ; EP1S10B672C6                          ;
; Total logic elements     ; 64 / 10,570 ( < 1 % )                 ;
; Total pins               ; 210 / 345 ( 60 % )                    ;
; Total memory bits        ; 0 / 920,448 ( 0 % )                   ;
; DSP block 9-bit elements ; 4 / 48 ( 8 % )                        ;
; Total PLLs               ; 0 / 6 ( 0 % )                         ;
; Total DLLs               ; 0 / 2 ( 0 % )                         ;
--------------------------------------------------------------------


-------------------------------------------------------------------
; Fitter Settings                                                 ;
-------------------------------------------------------------------
; Option                                     ; Setting            ;
-------------------------------------------------------------------
; Device                                     ; EP1S10B672C6       ;
; Fast Fit compilation                       ; Off                ;
; Optimize IOC register placement for timing ; On                 ;
; Optimize timing                            ; Normal Compilation ;
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; Fitter Device Options                                                   ;
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; Option                                       ; Setting                  ;
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; Auto-restart configuration after error       ; Off                      ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
---------------------------------------------------------------------------


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; Fitter Equations  ;
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The equations can be found in e:\whj\fft.fit.eqn.