fft.map.eqn

关于FFT实现的Verilog代码

--F6L32 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUT
--operation mode is arithmetic

F6L32 = CARRY(H2_result[10] & (H4_result[10] # !F6L12) # !H2_result[10] & H4_result[10] & !F6L12);


--F6_result[9] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[9]
--operation mode is arithmetic

F6_result[9]_carry_eqn = F6L91;
F6_result[9] = H2_result[9] $ H4_result[9] $ F6_result[9]_carry_eqn;

--F6L12 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT
--operation mode is arithmetic

F6L12 = CARRY(H2_result[9] & !H4_result[9] & !F6L91 # !H2_result[9] & (!F6L91 # !H4_result[9]));


--F6_result[8] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[8]
--operation mode is arithmetic

F6_result[8]_carry_eqn = F6L71;
F6_result[8] = H2_result[8] $ H4_result[8] $ !F6_result[8]_carry_eqn;

--F6L91 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUT
--operation mode is arithmetic

F6L91 = CARRY(H2_result[8] & (H4_result[8] # !F6L71) # !H2_result[8] & H4_result[8] & !F6L71);


--F6_result[7] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[7]
--operation mode is arithmetic

F6_result[7]_carry_eqn = F6L51;
F6_result[7] = H2_result[7] $ H4_result[7] $ F6_result[7]_carry_eqn;

--F6L71 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUT
--operation mode is arithmetic

F6L71 = CARRY(H2_result[7] & !H4_result[7] & !F6L51 # !H2_result[7] & (!F6L51 # !H4_result[7]));


--F6_result[6] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6]
--operation mode is arithmetic

F6_result[6]_carry_eqn = F6L31;
F6_result[6] = H2_result[6] $ H4_result[6] $ !F6_result[6]_carry_eqn;

--F6L51 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT
--operation mode is arithmetic

F6L51 = CARRY(H2_result[6] & (H4_result[6] # !F6L31) # !H2_result[6] & H4_result[6] & !F6L31);


--F6_result[5] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[5]
--operation mode is arithmetic

F6_result[5]_carry_eqn = F6L11;
F6_result[5] = H2_result[5] $ H4_result[5] $ F6_result[5]_carry_eqn;

--F6L31 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT
--operation mode is arithmetic

F6L31 = CARRY(H2_result[5] & !H4_result[5] & !F6L11 # !H2_result[5] & (!F6L11 # !H4_result[5]));


--F6_result[4] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[4]
--operation mode is arithmetic

F6_result[4]_carry_eqn = F6L9;
F6_result[4] = H2_result[4] $ H4_result[4] $ !F6_result[4]_carry_eqn;

--F6L11 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT
--operation mode is arithmetic

F6L11 = CARRY(H2_result[4] & (H4_result[4] # !F6L9) # !H2_result[4] & H4_result[4] & !F6L9);


--F6_result[3] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[3]
--operation mode is arithmetic

F6_result[3]_carry_eqn = F6L7;
F6_result[3] = H2_result[3] $ H4_result[3] $ F6_result[3]_carry_eqn;

--F6L9 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT
--operation mode is arithmetic

F6L9 = CARRY(H2_result[3] & !H4_result[3] & !F6L7 # !H2_result[3] & (!F6L7 # !H4_result[3]));


--F6_result[2] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[2]
--operation mode is arithmetic

F6_result[2]_carry_eqn = F6L5;
F6_result[2] = H2_result[2] $ H4_result[2] $ !F6_result[2]_carry_eqn;

--F6L7 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT
--operation mode is arithmetic

F6L7 = CARRY(H2_result[2] & (H4_result[2] # !F6L5) # !H2_result[2] & H4_result[2] & !F6L5);


--F6_result[1] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic

F6_result[1]_carry_eqn = F6L3;
F6_result[1] = H2_result[1] $ H4_result[1] $ F6_result[1]_carry_eqn;

--F6L5 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic

F6L5 = CARRY(H2_result[1] & !H4_result[1] & !F6L3 # !H2_result[1] & (!F6L3 # !H4_result[1]));


--F6_result[0] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

F6_result[0] = H2_result[0] $ H4_result[0];

--F6L3 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

F6L3 = CARRY(H2_result[0] & H4_result[0]);


--F5_result[15] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[15]
--operation mode is normal

F5_result[15]_carry_eqn = F5L13;
F5_result[15] = H1_result[15] $ H3_result[15] $ !F5_result[15]_carry_eqn;


--F5_result[14] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[14]
--operation mode is arithmetic

F5_result[14]_carry_eqn = F5L92;
F5_result[14] = H1_result[14] $ H3_result[14] $ F5_result[14]_carry_eqn;

--F5L13 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[14]~COUT
--operation mode is arithmetic

F5L13 = CARRY(H1_result[14] & H3_result[14] & !F5L92 # !H1_result[14] & (H3_result[14] # !F5L92));


--F5_result[13] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[13]
--operation mode is arithmetic

F5_result[13]_carry_eqn = F5L72;
F5_result[13] = H1_result[13] $ H3_result[13] $ !F5_result[13]_carry_eqn;

--F5L92 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUT
--operation mode is arithmetic

F5L92 = CARRY(H1_result[13] & (!F5L72 # !H3_result[13]) # !H1_result[13] & !H3_result[13] & !F5L72);


--F5_result[12] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[12]
--operation mode is arithmetic

F5_result[12]_carry_eqn = F5L52;
F5_result[12] = H1_result[12] $ H3_result[12] $ F5_result[12]_carry_eqn;

--F5L72 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUT
--operation mode is arithmetic

F5L72 = CARRY(H1_result[12] & H3_result[12] & !F5L52 # !H1_result[12] & (H3_result[12] # !F5L52));


--F5_result[11] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[11]
--operation mode is arithmetic

F5_result[11]_carry_eqn = F5L32;
F5_result[11] = H1_result[11] $ H3_result[11] $ !F5_result[11]_carry_eqn;

--F5L52 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUT
--operation mode is arithmetic

F5L52 = CARRY(H1_result[11] & (!F5L32 # !H3_result[11]) # !H1_result[11] & !H3_result[11] & !F5L32);


--F5_result[10] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[10]
--operation mode is arithmetic

F5_result[10]_carry_eqn = F5L12;
F5_result[10] = H1_result[10] $ H3_result[10] $ F5_result[10]_carry_eqn;

--F5L32 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUT
--operation mode is arithmetic

F5L32 = CARRY(H1_result[10] & H3_result[10] & !F5L12 # !H1_result[10] & (H3_result[10] # !F5L12));


--F5_result[9] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[9]
--operation mode is arithmetic

F5_result[9]_carry_eqn = F5L91;
F5_result[9] = H1_result[9] $ H3_result[9] $ !F5_result[9]_carry_eqn;

--F5L12 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT
--operation mode is arithmetic

F5L12 = CARRY(H1_result[9] & (!F5L91 # !H3_result[9]) # !H1_result[9] & !H3_result[9] & !F5L91);


--F5_result[8] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[8]
--operation mode is arithmetic

F5_result[8]_carry_eqn = F5L71;
F5_result[8] = H1_result[8] $ H3_result[8] $ F5_result[8]_carry_eqn;

--F5L91 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUT
--operation mode is arithmetic

F5L91 = CARRY(H1_result[8] & H3_result[8] & !F5L71 # !H1_result[8] & (H3_result[8] # !F5L71));


--F5_result[7] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[7]
--operation mode is arithmetic

F5_result[7]_carry_eqn = F5L51;
F5_result[7] = H1_result[7] $ H3_result[7] $ !F5_result[7]_carry_eqn;

--F5L71 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUT
--operation mode is arithmetic

F5L71 = CARRY(H1_result[7] & (!F5L51 # !H3_result[7]) # !H1_result[7] & !H3_result[7] & !F5L51);


--F5_result[6] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6]
--operation mode is arithmetic

F5_result[6]_carry_eqn = F5L31;
F5_result[6] = H1_result[6] $ H3_result[6] $ F5_result[6]_carry_eqn;

--F5L51 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT
--operation mode is arithmetic

F5L51 = CARRY(H1_result[6] & H3_result[6] & !F5L31 # !H1_result[6] & (H3_result[6] # !F5L31));


--F5_result[5] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[5]
--operation mode is arithmetic

F5_result[5]_carry_eqn = F5L11;
F5_result[5] = H1_result[5] $ H3_result[5] $ !F5_result[5]_carry_eqn;

--F5L31 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT
--operation mode is arithmetic

F5L31 = CARRY(H1_result[5] & (!F5L11 # !H3_result[5]) # !H1_result[5] & !H3_result[5] & !F5L11);


--F5_result[4] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[4]
--operation mode is arithmetic

F5_result[4]_carry_eqn = F5L9;
F5_result[4] = H1_result[4] $ H3_result[4] $ F5_result[4]_carry_eqn;

--F5L11 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT
--operation mode is arithmetic

F5L11 = CARRY(H1_result[4] & H3_result[4] & !F5L9 # !H1_result[4] & (H3_result[4] # !F5L9));


--F5_result[3] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[3]
--operation mode is arithmetic

F5_result[3]_carry_eqn = F5L7;
F5_result[3] = H1_result[3] $ H3_result[3] $ !F5_result[3]_carry_eqn;

--F5L9 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT
--operation mode is arithmetic

F5L9 = CARRY(H1_result[3] & (!F5L7 # !H3_result[3]) # !H1_result[3] & !H3_result[3] & !F5L7);


--F5_result[2] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[2]
--operation mode is arithmetic

F5_result[2]_carry_eqn = F5L5;
F5_result[2] = H1_result[2] $ H3_result[2] $ F5_result[2]_carry_eqn;

--F5L7 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT
--operation mode is arithmetic

F5L7 = CARRY(H1_result[2] & H3_result[2] & !F5L5 # !H1_result[2] & (H3_result[2] # !F5L5));


--F5_result[1] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic

F5_result[1]_carry_eqn = F5L3;
F5_result[1] = H1_result[1] $ H3_result[1] $ !F5_result[1]_carry_eqn;

--F5L5 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic

F5L5 = CARRY(H1_result[1] & (!F5L3 # !H3_result[1]) # !H1_result[1] & !H3_result[1] & !F5L3);


--F5_result[0] is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

F5_result[0] = H1_result[0] $ H3_result[0];

--F5L3 is lpm_add_sub_16:out1_out2|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

F5L3 = CARRY(H3_result[0] # !H1_result[0]);


--H2_mac_mult2 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2
--DSP Block Multiplier Base Width: 9-bits
H2_mac_mult2_a_data = DATA(x2_im[7], x2_im[6], x2_im[5], x2_im[4], x2_im[3], x2_im[2], x2_im[1], x2_im[0]);
H2_mac_mult2_a_rep = UNSIGNED(H2_mac_mult2_a_data);
H2_mac_mult2_b_data = DATA(w_re[7], w_re[6], w_re[5], w_re[4], w_re[3], w_re[2], w_re[1], w_re[0]);
H2_mac_mult2_b_rep = UNSIGNED(H2_mac_mult2_b_data);
H2_mac_mult2_result = H2_mac_mult2_a_rep * H2_mac_mult2_b_rep;
H2_mac_mult2 = H2_mac_mult2_result[0];

--H2L2 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT1
H2L2 = H2_mac_mult2_result[1];

--H2L3 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT2
H2L3 = H2_mac_mult2_result[2];

--H2L4 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT3
H2L4 = H2_mac_mult2_result[3];

--H2L5 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT4
H2L5 = H2_mac_mult2_result[4];

--H2L6 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT5
H2L6 = H2_mac_mult2_result[5];

--H2L7 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT6
H2L7 = H2_mac_mult2_result[6];

--H2L8 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT7
H2L8 = H2_mac_mult2_result[7];

--H2L9 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT8
H2L9 = H2_mac_mult2_result[8];

--H2L01 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT9
H2L01 = H2_mac_mult2_result[9];

--H2L11 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT10
H2L11 = H2_mac_mult2_result[10];

--H2L21 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT11
H2L21 = H2_mac_mult2_result[11];

--H2L31 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT12
H2L31 = H2_mac_mult2_result[12];

--H2L41 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT13
H2L41 = H2_mac_mult2_result[13];

--H2L51 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT14
H2L51 = H2_mac_mult2_result[14];

--H2L61 is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2~DATAOUT15
H2L61 = H2_mac_mult2_result[15];


--H2_result[0] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[0]
--DSP Block Operation Mode: Simple Multiplier (9-bit)
H2_result[0] = H2_mac_mult2;

--H2_result[1] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[1]
H2_result[1] = H2L2;

--H2_result[2] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[2]
H2_result[2] = H2L3;

--H2_result[3] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[3]
H2_result[3] = H2L4;

--H2_result[4] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[4]
H2_result[4] = H2L5;

--H2_result[5] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[5]
H2_result[5] = H2L6;

--H2_result[6] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[6]
H2_result[6] = H2L7;

--H2_result[7] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[7]
H2_result[7] = H2L8;

--H2_result[8] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[8]
H2_result[8] = H2L9;

--H2_result[9] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[9]
H2_result[9] = H2L01;

--H2_result[10] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[10]
H2_result[10] = H2L11;

--H2_result[11] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[11]
H2_result[11] = H2L21;

--H2_result[12] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[12]
H2_result[12] = H2L31;

--H2_result[13] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[13]
H2_result[13] = H2L41;

--H2_result[14] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[14]
H2_result[14] = H2L51;

--H2_result[15] is lpm_mula:mult_x2_w_im_re|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|result[15]
H2_result[15] = H2L61;


--H4_mac_mult2 is lpm_mula:mult_x2_w_re_im|lpm_mult:lpm_mult_component|mult_6bk:auto_generated|mac_mult2
--DSP Block Multiplier Base Width: 9-bits
H4_mac_mult2_a_data = DATA(x2_re[7], x2_re[6], x2_re[5], x2_re[4], x2_re[3], x2_re[2], x2_re[1], x2_re[0]);
H4_mac_mult2_a_rep = UNSIGNED(H4_mac_mult2_a_data);
H4_mac_mult2_b_data = DATA(w_im[7], w_im[6], w_im[5], w_im[4], w_im[3], w_im[2], w_im[1], w_im[0]);