fft.map.rpt

关于FFT实现的Verilog代码

Analysis & Synthesis report for fft compilation.
Sun Oct 29 21:22:49 2006
Version 3.0 Build 199 06/26/2003 SJ Full Version

Command: quartus_map --import_settings_files=on --export_settings_files=off fft -c fft



---------------------
; Table of Contents ;
---------------------
   1. Legal Notice
   2. Flow Summary
   3. Flow Settings
   4. Flow Elapsed Time
   5. Analysis & Synthesis Summary
   6. Analysis & Synthesis Settings
   7. Hierarchy
   8. Analysis & Synthesis Resource Utilization by Entity
   9. Analysis & Synthesis Equations
  10. Analysis & Synthesis Messages


----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



--------------------------------------------------------------------
; Flow Summary                                                     ;
--------------------------------------------------------------------
; Flow Status              ; Successful - Sun Oct 29 21:22:49 2006 ;
; Compiler Setting Name    ; fft                                   ;
; Top-level Entity Name    ; fft                                   ;
; Family                   ; Stratix                               ;
; Device                   ; EP1S10B672C6                          ;
; Total logic elements     ; 96                                    ;
; Total pins               ; 210                                   ;
; Total memory bits        ; 0                                     ;
; DSP block 9-bit elements ; 4                                     ;
; Total PLLs               ; 0                                     ;
; Total DLLs               ; 0                                     ;
--------------------------------------------------------------------


-----------------------------------------------
; Flow Settings                               ;
-----------------------------------------------
; Option                ; Setting             ;
-----------------------------------------------
; Start date & time     ; 10/29/2006 21:22:46 ;
; Main task             ; Compilation         ;
; Compiler Setting Name ; fft                 ;
-----------------------------------------------


---------------------------------------
; Flow Elapsed Time                   ;
---------------------------------------
; Module Name          ; Elapsed Time ;
---------------------------------------
; Analysis & Synthesis ; 00:00:02     ;
; Total                ; 00:00:02     ;
---------------------------------------


-----------------------------------------------------------------------
; Analysis & Synthesis Summary                                        ;
-----------------------------------------------------------------------
; Analysis & Synthesis Status ; Successful - Sun Oct 29 21:22:48 2006 ;
; Compiler Setting Name       ; fft                                   ;
; Top-level Entity Name       ; fft                                   ;
; Family                      ; Stratix                               ;
; Total logic elements        ; 96                                    ;
; Total pins                  ; 210                                   ;
; Total memory bits           ; 0                                     ;
; DSP block 9-bit elements    ; 4                                     ;
; Total PLLs                  ; 0                                     ;
; Total DLLs                  ; 0                                     ;
-----------------------------------------------------------------------


-----------------------------------------------------------
; Analysis & Synthesis Settings                           ;
-----------------------------------------------------------
; Option                                        ; Setting ;
-----------------------------------------------------------
; Use Generated Physical Constraints File       ; On      ;
; Physical Synthesis Level for Resynthesis      ; Normal  ;
; Resynthesis Optimization Effort               ; Normal  ;
; Type of Retiming Performed During Resynthesis ; Full    ;
; Perform gate-level register retiming          ; Off     ;
; Perform WYSIWYG primitive resynthesis         ; Off     ;
; Focus entity name                             ; |fft    ;
; Family name                                   ; Stratix ;
; Preserve fewer node names                     ; On      ;
; Disk space/compilation speed tradeoff         ; Normal  ;
-----------------------------------------------------------