minsecondb.vhd

整点闹钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINSECONDb is
port(clk,clrm,stop:in std_logic;----时钟/清零信号
     secm1,secm0:out std_logic_vector(3 downto 0);----秒高位/低位
     co:out std_logic);-------输出/进位信号
end MINSECONDb;

architecture SEC of MINSECONDb is
signal clk1,DOUT2:std_logic;

begin
process(clk,clrm)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
   VARIABLE COUNT2 :INTEGER RANGE 0 TO 10 ;
begin

IF CLK'EVENT AND CLK='1'THEN
      IF COUNT2>=0 AND COUNT2<10 THEN
         COUNT2:=COUNT2+1;
      ELSE COUNT2:=0;
           DOUT2<= NOT DOUT2;
      END IF;
   END IF;

if clrm='1' then----当clr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
   if stop='1' then
      cnt0:=cnt0;
      cnt1:=cnt1;
      end if;

if cnt1="1001" and cnt0="1000" then----当记数为98（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
--elsif cnt0="1001" then
--clk1<=not clk1;
else
cnt0:="0000";

if cnt1<"1001" then----高位小于9时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
secm1<=cnt1;
secm0<=cnt0;

end process;
end SEC;