alert.vhd

整点闹钟

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);------输入秒、分高/低位信号
    clk:in std_logic;------高频声控制
    q500,qlk:out std_logic);----低频声控制
end ALERT;

architecture sss_arc of ALERT is
  begin
  process(clk)
  begin

  if clk'event and clk='1' then
    if m1="0101" and m0="1001" and s1="0101" then----当秒高位为5，低位为9时且分高位为5
      if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为1或3或5或7时
      q500<='1';----低频输出为1
      else
      q500<='0';----否则输出为0
      end if;
    end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
     qlk<='1';-----高频输出为1
     else
     qlk<='0';
     end if;
end if;
 end process;
 end sss_arc;