alert.vhd

整点闹钟

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
    clk:in std_logic;
    q500,qlk:out std_logic);
end ALERT;

architecture sss_arc of ALERT is
  begin
  process(clk)
  begin

  if clk'event and clk='1' then
    if m1="0101" and m0="1001" and s1="0101" then
      if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
      q500<='1';
      else
  q500<='0';
      end if;
    end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then
qlk<='1';
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;