control.vhd

VHDL写的大部分程序。希望大家一起学习

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY control IS
PORT(clk : IN STD_LOGIC;
	 sign : IN STD_LOGIC;
	 class : IN INTEGER RANGE 0 TO 7;  --量程编号
	 clk_out : OUT STD_LOGIC;   --周期测量计数器时钟
	 gate   : OUT STD_LOGIC;
	 mode   : IN STD_LOGIC_VECTOR(1 DOWNTO 0));	--周期测量计数器闸门
END control;
ARCHITECTURE rtl OF control IS
	SIGNAL sign_1  	:STD_LOGIC; --待测信号10分频
	SIGNAL sign_2  	:STD_LOGIC; --待测信号100分频
	SIGNAL sign_3  	:STD_LOGIC; --待测信号1000分频
	SIGNAL sign_4  	:STD_LOGIC; --待测信号10000分频 
	SIGNAL sign_5  	:STD_LOGIC; --待测信号100000分频
	SIGNAL sign_6  	:STD_LOGIC; --待测信号1000000分频
	SIGNAL clk_1  	:STD_LOGIC; --时钟的10分频
	SIGNAL cnt2		:INTEGER  RANGE 0 TO 9;
	COMPONENT counter_bcd7
		PORT(clr,ena,clk          	 : IN STD_LOGIC;   --clr计数器清零，en计数使能，clk时钟
			 q      				 : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);--计数器输出，该语句用于实际应用
			 --q      				 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);--计数器输出，该语句用于仿真
			 zeros	 			     : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
			 cout					 : OUT STD_LOGIC); --计数器进位
	END COMPONENT;
	SIGNAL low    : STD_LOGIC;   --常低电平
	SIGNAL high   : STD_LOGIC;   --常高电平
	SIGNAL q_sig      : STD_LOGIC_VECTOR(27 DOWNTO 0);  --7位BCD计数器输出
	SIGNAL zeros_sig  : STD_LOGIC_VECTOR(6 DOWNTO 0);   --7位BCD计数器输出ZEROS
    SIGNAL cout_sig   : STD_LOGIC;						--7位BCD计数器输出COUT
	SIGNAL gate_mul2  : STD_LOGIC;						--闸门信号的2倍频
	SIGNAL gate_sig   : STD_LOGIC;						--闸门信号
	SIGNAL clk_mode01  : STD_LOGIC;                    --周期和频率测量模式下的计数器时钟
	SIGNAL gate_mode01  : STD_LOGIC;                    --周期和频率测量模式下的计数器闸门
BEGIN
	low <= '0';
	high <= '1';
	--时钟的10分频
	PROCESS(clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			IF(cnt2 = cnt2'high)THEN
				cnt2 <= 0;
				clk_1 <= '1';
			ELSE
				cnt2 <= cnt2 +1;
				clk_1 <= '0';
			END IF;
		END IF;
	END PROCESS;
	--7位BCD计数器
	counter_control: counter_bcd7 
		PORT MAP (clr => low,
				  ena => high,
				  clk => sign,
				  q => q_sig, 
		          zeros => zeros_sig,
				  cout => cout_sig);
	sign_1 <= zeros_sig(0);
	sign_2 <= zeros_sig(1);
	sign_3 <= zeros_sig(2);
	sign_4 <= zeros_sig(3);
	sign_5 <= zeros_sig(4);
	sign_6 <= zeros_sig(5);
	--多路选通器
	PROCESS(class,clk,clk_1,sign,sign_1,sign_2,sign_3,sign_4,sign_5,sign_6,mode)
	BEGIN
			CASE class IS
				WHEN 0 => 	
							clk_mode01 <= clk_1;
							gate_mul2 <= sign;
				WHEN 1 =>  
							clk_mode01 <= clk;
							gate_mul2 <= sign;					
				WHEN 2 =>
							clk_mode01 <= clk;
							gate_mul2 <= sign_1;
				WHEN 3 =>
							clk_mode01 <= clk;
							gate_mul2 <= sign_2;
				WHEN 4 =>
							clk_mode01 <= clk;
							gate_mul2 <= sign_3;
				WHEN 5 =>
							clk_mode01 <= clk;
							gate_mul2 <= sign_4;
				WHEN 6 =>
							clk_mode01 <= clk;
							gate_mul2 <= sign_5;
				WHEN 7 =>
							clk_mode01 <= clk;
							gate_mul2 <= sign_6;
				WHEN OTHERS => 
							clk_mode01 <= clk;
							gate_mul2 <= sign;
			END CASE;
	END PROCESS;
	--二分频
	PROCESS(gate_mul2)
	BEGIN
		IF(gate_mul2'event AND gate_mul2='1')THEN
			gate_sig <= not gate_sig;
		END IF;
	END PROCESS;
	--选择器
	PROCESS(gate_sig,mode)
	BEGIN
		IF mode/="10" THEN
			--周期和频率测量工作方式
			clk_out <= clk_mode01;
			gate <= gate_sig;
		ELSE
			--脉冲宽度测量方式
				clk_out <= clk;
				gate <= sign;
		END IF;
	END PROCESS;
END rtl;