shift_siso.vhd

VHDL写的大部分程序。希望大家一起学习

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY shift_siso IS
   GENERIC(x : INTEGER := 8);      --移位寄存器宽度
   PORt(
        --clk时钟，reset复位，direct移位方向,se移位使能，si串行输入
      	clk,reset,direct,se,si	: IN std_logic;   
		so		: OUT std_logic      --so串行输出
   );
END shift_siso;
ARCHITECTURE rtl OF shift_siso IS
   SIGNAL reg : STD_LOGIC_VECTOR((x-1) DOWNTO 0);
BEGIN
   PROCESS(clk,reset)
   BEGIN
	  --异步复位
      IF (reset = '1') THEN
         reg<= (OTHERS => '0');
      ELSIF clk'event AND clk = '1' THEN
         IF (se = '1') AND (direct = '1') THEN 
          --右移一位      
            reg(x-1) <= si;
            reg((x-2) downto 0) <= reg((x-1) DOWNTO 1);
	 	ELSIF (se = '1') AND (direct= '0') THEN
          --左移一位
	    	reg((x-1) DOWNTO 1) <= reg((x-2) DOWNTO 0);
            reg(0) <= si;
	 	END IF;
     END IF;
   END PROCESS;
   --串行输出进程
   PROCESS(direct,reg)
   BEGIN
		IF direct='1' THEN
   			so <= reg(0);
        ELSE
			so<=reg(x-1);
		END IF;
   END PROCESS;
END rtl;