mseq_sm.vhd

来自「VHDL写的大部分程序。希望大家一起学习」· VHDL 代码 · 共 45 行

LIBRARY IEEE; 
USE ieee.std_logic_1164.all ;
ENTITY mseq_sm IS
	PORT(
		clk		: IN	STD_logic;                          --时钟
		q	    : OUT	STD_logic_vector(2 DOWNTO 0));      --寄存器输出
END mseq_sm;
ARCHITECTURE behavier OF mseq_sm IS
	SIGNAL present_state: STD_logic_vector(2 downto 0);
	SIGNAL next_state: STD_logic_vector(2 downto 0);
BEGIN
	update :PROCESS(clk)			        --每个时钟上升沿，更新状态
    BEGIN
   	     IF (clk'EVENT AND clk='1') THEN     --状态更新
	 		present_state <= next_state;
	     END IF;
    END PROCESS update;

	statedecoder:PROCESS(present_state)					--状态译码
	BEGIN
		CASE present_state IS
			WHEN B"000" =>
					next_state <= B"001";
			WHEN B"001" =>
					next_state <= B"100";
			WHEN B"100" =>
					next_state <= B"010";
			WHEN B"010" =>
					next_state <= B"101";
			WHEN B"101" =>
					next_state <= B"110";
			WHEN B"110" =>
					next_state <= B"111";
			WHEN B"111" =>
					next_state <= B"011";
			WHEN B"011" =>
					next_state <= B"001";
			WHEN OTHERS =>						--多于状态处理
				    next_state <=B"000";
		END CASE;
	END PROCESS statedecoder;
	q<=present_state;     --输出译码
END behavier;