and2_truth_table.vhd

来自「VHDL写的大部分程序。希望大家一起学习」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and2_truth_table IS
PORT(
		a,b		: IN	STD_LOGIC;
		y	    : OUT	STD_LOGIC);
END and2_truth_table;
ARCHITECTURE behavier OF and2_truth_table IS
BEGIN
	truth_table:
	PROCESS (a,b)
		VARIABLE a_b : STD_LOGIC_VECTOR(1 DOWNTO 0); 
	BEGIN
		a_b:=a&b;				
		CASE a_b IS
			WHEN "00" =>y<='0';
			WHEN "01" =>y<='0';
			WHEN "10" =>y<='0';
			WHEN "11" =>y<='1';
			WHEN OTHERS => y<='X';
		END CASE;
	END PROCESS truth_table;
END behavier;