decoder4_10.vhd

来自「VHDL写的大部分程序。希望大家一起学习」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY decoder4_10 IS
		PORT(
		A   : IN	STD_LOGIC_VECTOR(3 downto 0);
		Y	: OUT	STD_LOGIC_vector(9 downto 0));
END decoder4_10;
ARCHITECTURE behavier OF decoder4_10 IS
BEGIN
process(A)
begin
	case A is
          when B"0000" => Y<=B"0111111111";
          when B"0001" => Y<=B"1011111111";
 		  when B"0010" => Y<=B"1101111111";
		  when B"0011" => Y<=B"1110111111";
		  when B"0100" => Y<=B"1111011111";
		  when B"0101" => Y<=B"1111101111";
		  when B"0110" => Y<=B"1111110111";
		  when B"0111" => Y<=B"1111111011";
		  when B"1000" => Y<=B"1111111101";
		  when B"1001" => Y<=B"1111111110";
		  when others  => Y<=B"1111111111";
   end case;
end process;
END behavier;