zhuangtaiji.vhd

来自「给出了一个简单明了描述状态机的方法,可以学到怎样用vhdl描述状态机」· VHDL 代码 · 共 52 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY zhuangtaiji IS
             PORT(reset,state_in  : IN  std_logic;
                  clk             : IN  std_logic;
                  clkout          : OUT std_logic);
END zhuangtaiji;

ARCHITECTURE zhuangtaiji_rtl OF zhuangtaiji IS
TYPE state IS (st0,st1,st2,st3);
SIGNAL current_state, next_state : state;
BEGIN
    REG: PROCESS(clk)
         BEGIN
              IF(reset='1') THEN
                 current_state <= st0;
              ELSIF(clk'event AND clk='0') THEN
                 current_state <= next_state;
              END IF;
         END PROCESS REG;

    COM: PROCESS(current_state,state_in)
         BEGIN
              CASE current_state IS
                   WHEN st0 => clkout <= '0';--因为是常量所以能传输给端口带出进程
                       IF(state_in='0') THEN
                           next_state <=st1;
                       ELSE
                           next_state <=st3;
                       END IF;
                   WHEN st1 => clkout <= '0';
                       IF(state_in='0') THEN
                           next_state <=st2;
                       ELSE
                           next_state <=st0;
                       END IF;
                   WHEN st2 => clkout <= '0';
                       IF(state_in='0') THEN
                           next_state <=st3;
                       ELSE
                           next_state <=st1;
                       END IF;
                   WHEN st3 => clkout <='1';
                       IF(state_in='0') THEN
                           next_state <=st0;
                       ELSE
                           next_state <=st2;
                       END IF;
              END CASE;
          END PROCESS COM;
END zhuangtaiji_rtl;