main.c

The Lite Evaluation/Demonstration Kit is intended to illustrate use of the AN3042. The AN3042 is c

		// 860: That's all there is to it on the 860 side !!!
	}
*/

/*
	//////////////////////////////////////////////////////////////////
	Test FIFO filling the FIFO from the host side before reading it.
	//////////////////////////////////////////////////////////////////

	// Make sure ibp FIFO is empty (cleaned up for the next time).
	while ( i2oregp->ibp_ibf != 0xFFFFffff )	  // read from ibp !!!
		;

	i2oregp->himr = 0xFFFFffff;	   // Mask out
	i2oregp->limr = 0xFFFFffff;

	regp->lint = 0x0000ffff;       // Clear the I2O FIFO Overflow flags (and all other flags).
	temp = regp->lint;             // Read it so we can see it on the logic analyzer. 

	regp->hint = 0x0000ffff;       // Clear the I2O FIFO Overflow flags (and all other flags).
	temp = regp->hint;             // Read it so we can see it on the logic analyzer. 

	//  ... then do all multiple DWORD tests.
	while (1)				// Go til I2ODONE, reading from the ibp and writing back to the obp.
	{
		writeLED (5, FALSE);  // Show on the display that we're ready to do the multiple DWORD tests.
		// delay (100000);

		// Host writes 32+ DWORDS to the ibp.
		// 860: Spin waiting for ibp overflow. Wait forever.
		while ( 
				// ((regp->lint & 1) != 1) &&
				((regp->lint & 2) != 2) // &&
				// ((regp->hint & 1) != 1) &&
		        // ((regp->hint & 2) != 2)
		      )
			;
		
		writeLED (0xB, FALSE);

		// Read all ibp DWORDs until empty.
		// Caution: we must read exactly as here.  We only get one chance to read actual data.
		while ( (hostwrote = i2oregp->ibp_ibf) != 0xFFFFffff )	  // read from ibp !!!
		{
			// if (hostwrote == I2ODONE)
			//	break;				// Do some other test.
		
			i2oregp->obp_obf = hostwrote;	// write to obp  !!!
		}

		regp->lint = 2;		// Must clear the I2O PCI Overflow bit (else stays set forever, regardless of
							//  the state of the FIFO)
		temp = regp->lint;  // Read it so we can see it on the logic analyzer. 

		// if (hostwrote == I2ODONE)
		//	break;				// Do some other test.
		
		// 860: That's all there is to it on the 860 side !!!
	}

	// Make sure ibp FIFO is empty (cleaned up for the next time) before exiting.
	while ( i2oregp->ibp_ibf != 0xFFFFffff )	  // read from ibp !!!
		;

}  // end testI2O_2()
*/


//
// testI2O_3
//
//   This test uses the protocol 'all ones = empty FIFO' from the host side only
//    using the FIFO debug ports.
//
//
DWORD testI2O_3 (void)
{
	DWORD wrote, read, temp, i;
	
	// Test obp.
	
	//  Do not use the following technique to drain the FIFO.  It will fail if any prior process has written a 0xFFFFffff
	//  to the FIFO we're trying to drain !!!
	//
	//  while ((temp = i2oregp->fifo44.obp_debug) != 0xFFFFffff)    // Drain obp_debug, using 0xFFFFffff to indicate empty.
	//	  ;
	//
	// Instead, use the following count-based technique.  Takes a bit longer, but is safer.
	for (i = 0 ; i < FIFO_DEPTH+1; i++)
		temp = i2oregp->fifo44.obp_debug;	// Drain obp_debug using count (not trusting 0xFFFFffff = empty).

	wrote = 0xBBBA5500;
	for (i = 0 ; i < FIFO_DEPTH+1 ; i++)
		i2oregp->fifo4C.obp = wrote + i;	// Write obp

	for (i = 0 ; i < FIFO_DEPTH ; i++)
	{
		read = i2oregp->fifo44.obp_debug;	// Read obp_debug
		if (read != wrote + i)
		{
			errorHandler(0);
		}
	}


	// Test ibp
	for (i = 0 ; i < FIFO_DEPTH+1; i++)
		temp = i2oregp->fifo48.ibp;			 	// Drain ibp using count (not trusting 0xFFFFffff = empty).

	wrote = 0xABBABB00;
	for (i = 0 ; i < FIFO_DEPTH+1 ; i++)
		i2oregp->fifo40.ibp_debug = wrote + i;	// Write ibp_debug

	for (i = 0 ; i < FIFO_DEPTH ; i++)
	{
		read = i2oregp->fifo48.ibp;				// Read ibp
		if (read != wrote + i)
		{
			errorHandler(0);
		}
	}


	// Test ibf
	for (i = 0 ; i < FIFO_DEPTH+1; i++)
		temp = i2oregp->fifo40.ibf_debug;	 	// Drain ibf_debug using count (not trusting 0xFFFFffff = empty).

	wrote = 0xABFABF00;
	for (i = 0 ; i < FIFO_DEPTH+1 ; i++)
		i2oregp->fifo48.ibf = wrote + i;		// Write ibf

	for (i = 0 ; i < FIFO_DEPTH ; i++)
	{
		read = i2oregp->fifo40.ibf_debug;		// Read ibf_debug
		if (read != wrote + i)
		{
			errorHandler(0);
		}
	}


	// Test obp
	for (i = 0 ; i < FIFO_DEPTH+1; i++)
		temp = i2oregp->fifo4C.obf;			 	// Drain obf using count (not trusting 0xFFFFffff = empty).

	wrote = 0xBBFBBF00;
	for (i = 0 ; i < FIFO_DEPTH+1 ; i++)
		i2oregp->fifo44.obf_debug = wrote + i;	// Write obf_debug

	for (i = 0 ; i < FIFO_DEPTH ; i++)
	{
		read = i2oregp->fifo4C.obf;				// Read obf
		if (read != wrote + i)
		{
			errorHandler(0);
		}
	}

	return (errorCnt);

}  // end testI2O_3()


//
// testInterrupts
//
// 
DWORD testInterrupts (void)
{

 // Not quite finished :-) 		

}  // end testInterrrupts




#define DirAcc_IntAck			( 0 )	// Read
#define DirAcc_SpecialCycle		( 0	)	// Write

#define DirAcc_IO				( 1	)
#define DirAcc_Mem				( 2	)
#define DirAcc_Config			( 3	)

#define VendorID				( 0x00/4 )	// DWORD addresses
#define BAR0					( 0x10/4 )
#define BAR1					( 0x14/4 )

// Note well: The mapping between the card slots and the address bits in the Config Cycles below apply to our test PC.
//   Yours will probably be different.
#define OurAddr					0x02000000		// The address of the our (the 860's) board when plugged into the zeroth ??? slot
#define TargetAddr				0x08000000		// The address of the target board


testDirectAccess(void)
{
	DWORD i, temp, origbar0, bar1, bit;
	
	// RDYOUT# PAL allows us to do Reads, as well as Writes

/*
	bit = 0x80000000;
	for (i = 3 ; i < 10 ; i++)
	{
		regp->dahbase = (bit >> i)  | (DirAcc_Config << 1);	// Set up for Config Cycles		
		temp = *(DAregion + VendorID);						// Read
	}
*/
/*	   
	regp->dahbase = 0x20000000 | (DirAcc_Config << 1);	// Set up for Config Cycles		
	temp = *(DAregion + VendorID);						// Read

	regp->dahbase = 0x10000000 | (DirAcc_Config << 1);	// Set up for Config Cycles		
	temp = *(DAregion + VendorID);						// Read

	regp->dahbase = 0x08000000 | (DirAcc_Config << 1);	// Set up for Config Cycles		
	temp = *(DAregion + VendorID);						// Read

	regp->dahbase = 0x02000000 | (DirAcc_Config << 1);	// Set up for Config Cycles		
	temp = *(DAregion + VendorID);						// Read

	regp->dahbase = 0x01000000 | (DirAcc_Config << 1);	// Set up for Config Cycles		
	temp = *(DAregion + VendorID);						// Read

	regp->dahbase = 0x00800000 | (DirAcc_Config << 1);	// Set up for Config Cycles		
	temp = *(DAregion + VendorID);						// Read

 */

	regp->dahbase = TargetAddr | (DirAcc_Config << 1);	// Set up for Config Cycles
			
	origbar0 = *(DAregion + BAR0);	 	 // Read BAR 0


	*(DAregion + BAR0) = ~origbar0;		 // Write the complement

	temp = *(DAregion + BAR0);		 	 // Read it back
	
	if (temp != (~origbar0 & 0xFFFF8000) )				 // Check it.
	  errorHandler (0);


	*(DAregion + BAR0) = origbar0;		 // Write the original
	  
	temp = *(DAregion + BAR0);		 	 // Read it back
	
	if (temp != origbar0)				 // Check it.
	  errorHandler (0);

	// While we're set up for Config cycles, read BAR1.
	bar1 = *(DAregion + BAR1);

	// Do shared memory test into the target board (the 2nd 3042 board in the PC).
	// This test intentionally crosses the boundary between the 
	//   DA Region         (0x2000 to 0x3FFF)
	//   and Shared Memory (0x4000 to 0x7FFF).
	// If the PC has the right 3042 cards plugged in, that boundary *must* be invisible to this test.
	{
		DWORD tstBlkSz;
		DWORD i, dWrote;

		tstBlkSz = DAregionsize + 0x100;	    // 0x100 bytes into the Shared Mem.

		regp->dahbase = (origbar0 + SMbase) | (DirAcc_Mem << 1);	// Set up the Direct Access register for Memory Cycles, 
																	// and point to the Shared Memory of the target.
		// Non-complement first...
		for (i = 0; i < tstBlkSz/4; i++)		// Write address pattern
		{
			// ((long *) DAregion)[i] = ~i;		// For a wimpy, albeit fast, test.
			((long *) DAregion)[i] = i | (i << 12) | (i << 24);
		}

		for (i = 0; i < tstBlkSz/4; i++)		// Read and check address pattern
		{
			// dWrote = ~i;
			dWrote = i | (i << 12) | (i << 24);
			if ( ((long *) DAregion)[i] != dWrote)
			{
				errorHandler (0);
			}
		}


		// Then the complement...
		for (i = 0; i < tstBlkSz/4; i++)		// Write address pattern
		{
			((long *) DAregion)[i] = ~(i | (i << 12) | (i << 24));
		}

		for (i = 0; i < tstBlkSz/4; i++)		// Read and check address pattern
		{
			dWrote = ~(i | (i << 12) | (i << 24));
			if ( ((long *) DAregion)[i] != dWrote)
			{
				errorHandler (0);
			}
		}
	}


	// Test I/O cycles of the Target by accessing the Target's Shared Mem through BAR1.
	{
		DWORD tstBlkSz;
		DWORD i, dRead, dWrote, temp;

		DWORD residue = (bar1 & 0x1FFF)/4;	  // The part of the targets BAR1 that we can't fit into the 
										  //   PCI Base Address field of the dahbase register.
		tstBlkSz = SMsize;

		// Set up the Direct Access register for I/O Cycles to BAR1 of the target.
		temp = bar1 | (DirAcc_IO << 1);
		temp &= 0xFFFFFF0F;     // Force the 'Byte Enables' to low (active) 
		regp->dahbase = temp;

		// Non-complement first...
		for (i = 0; i < tstBlkSz/4; i++)		// Write address pattern
		{
			((long *) DAregion)[residue + 0] = i*4 + SMbase;				 // Write the Shared Mem address to the I/O Address Ptr of the target.
			((long *) DAregion)[residue + 1] = i | (i << 12) | (i << 24);	 // Write the data    to the I/O Data register of the target.
																 //  This write causes the target to perform the memory cycle.
		}

		for (i = 0; i < tstBlkSz/4; i++)		// Read and check address pattern
		{
			dWrote = i | (i << 12) | (i << 24);

			((long *) DAregion)[residue + 0] = i*4 + SMbase;	 // Write the Shared Mem address to the I/O Address Ptr of the target.
			dRead = ((long *) DAregion)[residue + 1];	         // Read the data     to the I/O Data register of the target.
																 //  This read causes the target to perform the memory cycle.
			if ( dRead != dWrote)
			{
				errorHandler (0);
			}
		}
		
	}


	// Int Ack       (valid for reads  only)
	regp->dahbase = (0) | (DirAcc_IntAck << 1);
	temp = *(DAregion);

	// Special Cycle (valid for writes only)
	regp->dahbase = (0) | (DirAcc_SpecialCycle << 1);
	*(DAregion) = temp;
				

/*
	//  A useful loop to scope out the RDYOUT PAL.  Via SoftICE, poke a good alternating data pattern into the
	//   first 2 DWORD of Shared Mem on the target board.
	while (1)
	{
	   temp = ((long *) DAregion)[0];
	   temp = ((long *) DAregion)[1];
	}
*/
}


long testLED (void)
{
	long count, temp, i;

	// while (1)  			//  for (i = 0 ; i < 10000 ; i++)
	{
		LEDvalue++;
		writeLED (LEDvalue, FALSE);

		// Wait loop
		// for (count = 0; count < 10000; count ++) 
			// temp = 0x11223344;
	}
}


main()
{
	initialize();

	// testSharedMemWithHost_W2();
	// initSharedMem(0);		   // Required for the guardband tests.

	// For Mutha Test, Initialize SM to a known pattern.  Is for dead blocks that should not change.
	// Is done here on the Local side, since we always start that first.
	initSharedMem(UNUSEDblockFROMlocal);

	while(1)
	{
		// testDirectAccess();
		// testOpRegs();
		// testSharedMem();
		// testSharedMemWithHost_R2();
		// testSharedMemWithHost_3();
		// testSMguardband_PL();

		// Mutha test.
		accessTrue_AsTarget();
		accessComplement_AsTarget();

		// testI2O();
		// testI2O_2();
		// testI2O_3();
		// testDMA();
		// testInterrupts();
		// testLED();
		indicateAlive();
	}

}