tcm0201.map.rpt

在公司做的TCM编解码程序

Info: Found 1 design units, including 1 entities, in source file bus2line.v
    Info: Found entity 1: bus2line
Info: Found 2 design units, including 1 entities, in source file parallel_series.vhd
    Info: Found design unit 1: parallel_series-behave
    Info: Found entity 1: parallel_series
Info: Found 2 design units, including 1 entities, in source file series_parallel.vhd
    Info: Found design unit 1: series_parallel-behave
    Info: Found entity 1: series_parallel
Info: Found 1 design units, including 1 entities, in source file change.bdf
    Info: Found entity 1: change
Info: Found 2 design units, including 1 entities, in source file DIDQ.vhd
    Info: Found design unit 1: DIDQ-behave
    Info: Found entity 1: DIDQ
Info: Found 1 design units, including 1 entities, in source file 3IN1.bdf
    Info: Found entity 1: 3IN1
Info: Found 1 design units, including 1 entities, in source file TCM0201.bdf
    Info: Found entity 1: TCM0201
Info: Found 1 design units, including 1 entities, in source file DEVIDE.bdf
    Info: Found entity 1: DEVIDE
Warning: (10273) Verilog HDL warning at para_out12.v(17): extended using "x" or "z"
Info: Found 1 design units, including 1 entities, in source file para_out12.v
    Info: Found entity 1: para_out12
Info: Found 1 design units, including 1 entities, in source file seri_para.v
    Info: Found entity 1: seri_para
Info: Found 2 design units, including 1 entities, in source file fs_out3.vhd
    Info: Found design unit 1: fs_out3-behave
    Info: Found entity 1: fs_out3
Info: Found 2 design units, including 1 entities, in source file series_para_store.vhd
    Info: Found design unit 1: series_para_store-behave
    Info: Found entity 1: series_para_store
Info: Found 1 design units, including 1 entities, in source file parallel_12out.v
    Info: Found entity 1: parallel_12out
Info: Found 1 design units, including 1 entities, in source file count.v
    Info: Found entity 1: count
Info: Elaborating entity "TCM0201" for the top level hierarchy
Warning: Primitive "NOT" of instance "inst15" not used
Warning: Primitive "NOT" of instance "inst16" not used
Info: Elaborating entity "DEVIDE" for hierarchy "DEVIDE:inst5"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/74393.bdf
    Info: Found entity 1: 74393
Info: Elaborating entity "74393" for hierarchy "DEVIDE:inst5|74393:176"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/7492.bdf
    Info: Found entity 1: 7492
Info: Elaborating entity "7492" for hierarchy "DEVIDE:inst5|7492:inst"
Info: Using design file CODEandIE.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: CODEandIE
Info: Elaborating entity "CODEandIE" for hierarchy "CODEandIE:inst2"
Warning: Port "A" of type 74161 and instance "inst18" is missing source signal
Warning: Port "D" of type 74161 and instance "inst18" is missing source signal
Warning: Port "B" of type 74161 and instance "inst18" is missing source signal
Warning: Port "C" of type 74161 and instance "inst18" is missing source signal
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/74161.tdf
    Info: Found entity 1: 74161
Info: Elaborating entity "74161" for hierarchy "CODEandIE:inst2|74161:inst18"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf
    Info: Found entity 1: p74161
Info: Elaborating entity "p74161" for hierarchy "CODEandIE:inst2|74161:inst18|p74161:sub"
Info: Elaborating entity "change" for hierarchy "change:inst4"
Info: Elaborating entity "parallel_series" for hierarchy "change:inst4|parallel_series:inst"
Warning: VHDL Process Statement warning at parallel_series.vhd(24): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at parallel_series.vhd(25): signal "digit_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at parallel_series.vhd(21): signal or variable "digit" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "digit" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "bus2line" for hierarchy "change:inst4|bus2line:inst4"
Info: Elaborating entity "series_parallel" for hierarchy "change:inst4|series_parallel:inst1"
Info: (10035) Verilog HDL or VHDL information at series_parallel.vhd(15): object "regb" declared but not used
Info: Elaborating entity "fs_out3" for hierarchy "change:inst4|fs_out3:inst9"
Warning: VHDL Process Statement warning at fs_out3.vhd(24): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fs_out3.vhd(25): signal "digit_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fs_out3.vhd(21): signal or variable "digit" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "digit" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file 3IN12.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: 3IN12
Info: Elaborating entity "3IN12" for hierarchy "3IN12:inst7"
Warning: Block or symbol "DFF" of instance "inst8" overlaps another block or symbol
Warning: Block or symbol "DFF" of instance "inst9" overlaps another block or symbol
Warning: Block or symbol "74151" of instance "inst15" overlaps another block or symbol
Warning: Port "D5" of type 74151 and instance "inst15" is missing source signal
Warning: Port "D0" of type 74151 and instance "inst15" is missing source signal
Warning: Port "D4" of type 74151 and instance "inst15" is missing source signal
Warning: Port "D6" of type 74151 and instance "inst15" is missing source signal
Warning: Port "D7" of type 74151 and instance "inst15" is missing source signal
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/74151.tdf
    Info: Found entity 1: 74151
Info: Elaborating entity "74151" for hierarchy "3IN12:inst7|74151:inst15"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/p74151.bdf
    Info: Found entity 1: p74151
Info: Elaborating entity "p74151" for hierarchy "3IN12:inst7|74151:inst15|p74151:sub"
Info: Elaborating entity "74161" for hierarchy "3IN12:inst7|74161:inst18"
Info: Elaborating entity "fenpin_36" for hierarchy "3IN12:inst7|fenpin_36:inst1"
Warning: Verilog HDL assignment warning at fenpin_36.v(11): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fenpin_36.v(12): truncated value with size 32 to match size of target (6)
Warning: Verilog HDL assignment warning at fenpin_36.v(15): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fenpin_36.v(16): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "para_out12" for hierarchy "para_out12:inst20"
Warning: Verilog HDL Always Construct warning at para_out12.v(14): variable "reg4" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at para_out12.v(15): variable "reg5" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at para_out12.v(16): variable "reg6" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Elaborating entity "series_para_store" for hierarchy "series_para_store:inst19"
Info: Inferred 4 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "series_para_store:inst19|n[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "series_para_store:inst22|n[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "series_para_store:inst23|n[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "change:inst4|series_parallel:inst1|n[0]~0"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 7 buffer(s)
    Info: Ignored 7 SOFT buffer(s)
Warning: Converting TRI node "CODEandIE:inst2|inst11" that feeds logic to an OR gate
Warning: Converting TRI node "CODEandIE:inst2|inst12" that feeds logic to an OR gate
Warning: Converting TRI node "CODEandIE:inst2|inst13" that feeds logic to an OR gate
Warning: Converting TRI node "CODEandIE:inst2|inst14" that feeds logic to an OR gate
Info: Duplicate registers merged to single register
    Info: Duplicate register "change:inst4|parallel_series:inst5|n[0]" merged to single register "change:inst4|parallel_series:inst|n[0]"
    Info: Duplicate register "series_para_store:inst22|lpm_counter:n_rtl_1|dffs[0]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[0]"
    Info: Duplicate register "series_para_store:inst23|lpm_counter:n_rtl_2|dffs[0]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[0]"
    Info: Duplicate register "change:inst4|parallel_series:inst5|n[1]" merged to single register "change:inst4|parallel_series:inst|n[1]"
    Info: Duplicate register "series_para_store:inst22|lpm_counter:n_rtl_1|dffs[1]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[1]"
    Info: Duplicate register "series_para_store:inst23|lpm_counter:n_rtl_2|dffs[1]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[1]"
    Info: Duplicate register "series_para_store:inst23|lpm_counter:n_rtl_2|dffs[2]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[2]"
    Info: Duplicate register "series_para_store:inst22|lpm_counter:n_rtl_1|dffs[2]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[2]"
    Info: Duplicate register "series_para_store:inst22|lpm_counter:n_rtl_1|dffs[3]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[3]"
    Info: Duplicate register "series_para_store:inst23|lpm_counter:n_rtl_2|dffs[3]" merged to single register "series_para_store:inst19|lpm_counter:n_rtl_0|dffs[3]"
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "CLK1" to global clock signal
Info: Implemented 288 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 39 output pins
    Info: Implemented 241 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
    Info: Processing ended: Mon Aug 20 16:08:18 2007
    Info: Elapsed time: 00:00:20