tcm0201.map.qmsg

在公司做的TCM编解码程序

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74151 3IN12:inst7\|74151:inst15 " "Info: Elaborating entity \"74151\" for hierarchy \"3IN12:inst7\|74151:inst15\"" {  } { { "3IN12.bdf" "inst15" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 208 760 880 432 "inst15" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/others/maxplus2/p74151.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/p74151.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 p74151 " "Info: Found entity 1: p74151" {  } { { "p74151.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74151.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p74151 3IN12:inst7\|74151:inst15\|p74151:sub " "Info: Elaborating entity \"p74151\" for hierarchy \"3IN12:inst7\|74151:inst15\|p74151:sub\"" {  } { { "74151.tdf" "sub" { Text "f:/altera/quartus50/libraries/others/maxplus2/74151.tdf" 26 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74161 3IN12:inst7\|74161:inst18 " "Info: Elaborating entity \"74161\" for hierarchy \"3IN12:inst7\|74161:inst18\"" {  } { { "3IN12.bdf" "inst18" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 480 528 648 664 "inst18" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin_36 3IN12:inst7\|fenpin_36:inst1 " "Info: Elaborating entity \"fenpin_36\" for hierarchy \"3IN12:inst7\|fenpin_36:inst1\"" {  } { { "3IN12.bdf" "inst1" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 736 312 408 832 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fenpin_36.v(11) " "Warning: Verilog HDL assignment warning at fenpin_36.v(11): truncated value with size 32 to match size of target (1)" {  } { { "fenpin_36.v" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/fenpin_36.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 fenpin_36.v(12) " "Warning: Verilog HDL assignment warning at fenpin_36.v(12): truncated value with size 32 to match size of target (6)" {  } { { "fenpin_36.v" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/fenpin_36.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fenpin_36.v(15) " "Warning: Verilog HDL assignment warning at fenpin_36.v(15): truncated value with size 32 to match size of target (1)" {  } { { "fenpin_36.v" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/fenpin_36.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 fenpin_36.v(16) " "Warning: Verilog HDL assignment warning at fenpin_36.v(16): truncated value with size 32 to match size of target (6)" {  } { { "fenpin_36.v" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/fenpin_36.v" 16 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "para_out12 para_out12:inst20 " "Info: Elaborating entity \"para_out12\" for hierarchy \"para_out12:inst20\"" {  } { { "TCM0201.bdf" "inst20" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { -336 1200 1384 -208 "inst20" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "reg4 para_out12.v(14) " "Warning: Verilog HDL Always Construct warning at para_out12.v(14): variable \"reg4\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "para_out12.v" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/para_out12.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "reg5 para_out12.v(15) " "Warning: Verilog HDL Always Construct warning at para_out12.v(15): variable \"reg5\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "para_out12.v" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/para_out12.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "reg6 para_out12.v(16) " "Warning: Verilog HDL Always Construct warning at para_out12.v(16): variable \"reg6\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "para_out12.v" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/para_out12.v" 16 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "series_para_store series_para_store:inst19 " "Info: Elaborating entity \"series_para_store\" for hierarchy \"series_para_store:inst19\"" {  } { { "TCM0201.bdf" "inst19" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { -464 616 768 -368 "inst19" "" } } } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "4 " "Info: Inferred 4 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "series_para_store:inst19\|n\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"series_para_store:inst19\|n\[0\]~0\"" {  } { { "series_para_store.vhd" "n\[0\]~0" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_para_store.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "series_para_store:inst22\|n\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"series_para_store:inst22\|n\[0\]~0\"" {  } { { "series_para_store.vhd" "n\[0\]~0" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_para_store.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "series_para_store:inst23\|n\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"series_para_store:inst23\|n\[0\]~0\"" {  } { { "series_para_store.vhd" "n\[0\]~0" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_para_store.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "change:inst4\|series_parallel:inst1\|n\[0\]~0 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"change:inst4\|series_parallel:inst1\|n\[0\]~0\"" {  } { { "series_parallel.vhd" "n\[0\]~0" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_parallel.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "7 " "Info: Ignored 7 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "7 " "Info: Ignored 7 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "CODEandIE:inst2\|inst11 " "Warning: Converting TRI node \"CODEandIE:inst2\|inst11\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "CODEandIE:inst2\|inst12 " "Warning: Converting TRI node \"CODEandIE:inst2\|inst12\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "CODEandIE:inst2\|inst13 " "Warning: Converting TRI node \"CODEandIE:inst2\|inst13\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "CODEandIE:inst2\|inst14 " "Warning: Converting TRI node \"CODEandIE:inst2\|inst14\" that feeds logic to an OR gate" {  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "change:inst4\|parallel_series:inst5\|n\[0\] change:inst4\|parallel_series:inst\|n\[0\] " "Info: Duplicate register \"change:inst4\|parallel_series:inst5\|n\[0\]\" merged to single register \"change:inst4\|parallel_series:inst\|n\[0\]\"" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[0\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[0\] " "Info: Duplicate register \"series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[0\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[0\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[0\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[0\] " "Info: Duplicate register \"series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[0\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[0\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "change:inst4\|parallel_series:inst5\|n\[1\] change:inst4\|parallel_series:inst\|n\[1\] " "Info: Duplicate register \"change:inst4\|parallel_series:inst5\|n\[1\]\" merged to single register \"change:inst4\|parallel_series:inst\|n\[1\]\"" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[1\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[1\] " "Info: Duplicate register \"series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[1\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[1\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[1\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[1\] " "Info: Duplicate register \"series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[1\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[1\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[2\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[2\] " "Info: Duplicate register \"series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[2\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[2\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[2\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[2\] " "Info: Duplicate register \"series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[2\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[2\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[3\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[3\] " "Info: Duplicate register \"series_para_store:inst22\|lpm_counter:n_rtl_1\|dffs\[3\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[3\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[3\] series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[3\] " "Info: Duplicate register \"series_para_store:inst23\|lpm_counter:n_rtl_2\|dffs\[3\]\" merged to single register \"series_para_store:inst19\|lpm_counter:n_rtl_0\|dffs\[3\]\"" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK1 " "Info: Promoted clock signal driven by pin \"CLK1\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "288 " "Info: Implemented 288 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "39 " "Info: Implemented 39 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "241 " "Info: Implemented 241 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 20 16:08:18 2007 " "Info: Processing ended: Mon Aug 20 16:08:18 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Info: Elapsed time: 00:00:20" {  } {  } 0}  } {  } 0}