tcm0201.map.qmsg

在公司做的TCM编解码程序

{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D 74161 inst18 " "Warning: Port \"D\" of type 74161 and instance \"inst18\" is missing source signal" {  } { { "CODEandIE.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 728 688 808 912 "inst18" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "B 74161 inst18 " "Warning: Port \"B\" of type 74161 and instance \"inst18\" is missing source signal" {  } { { "CODEandIE.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 728 688 808 912 "inst18" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "C 74161 inst18 " "Warning: Port \"C\" of type 74161 and instance \"inst18\" is missing source signal" {  } { { "CODEandIE.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 728 688 808 912 "inst18" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/others/maxplus2/74161.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/74161.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 74161 " "Info: Found entity 1: 74161" {  } { { "74161.tdf" "" { Text "f:/altera/quartus50/libraries/others/maxplus2/74161.tdf" 13 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74161 CODEandIE:inst2\|74161:inst18 " "Info: Elaborating entity \"74161\" for hierarchy \"CODEandIE:inst2\|74161:inst18\"" {  } { { "CODEandIE.bdf" "inst18" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 728 688 808 912 "inst18" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 p74161 " "Info: Found entity 1: p74161" {  } { { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p74161 CODEandIE:inst2\|74161:inst18\|p74161:sub " "Info: Elaborating entity \"p74161\" for hierarchy \"CODEandIE:inst2\|74161:inst18\|p74161:sub\"" {  } { { "74161.tdf" "sub" { Text "f:/altera/quartus50/libraries/others/maxplus2/74161.tdf" 35 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "change change:inst4 " "Info: Elaborating entity \"change\" for hierarchy \"change:inst4\"" {  } { { "TCM0201.bdf" "inst4" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { -48 480 592 80 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "parallel_series change:inst4\|parallel_series:inst " "Info: Elaborating entity \"parallel_series\" for hierarchy \"change:inst4\|parallel_series:inst\"" {  } { { "change.bdf" "inst" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 184 472 632 280 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset parallel_series.vhd(24) " "Warning: VHDL Process Statement warning at parallel_series.vhd(24): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "digit_in parallel_series.vhd(25) " "Warning: VHDL Process Statement warning at parallel_series.vhd(25): signal \"digit_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "digit parallel_series.vhd(21) " "Warning: VHDL Process Statement warning at parallel_series.vhd(21): signal or variable \"digit\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"digit\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 21 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bus2line change:inst4\|bus2line:inst4 " "Info: Elaborating entity \"bus2line\" for hierarchy \"change:inst4\|bus2line:inst4\"" {  } { { "change.bdf" "inst4" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 344 64 240 792 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "series_parallel change:inst4\|series_parallel:inst1 " "Info: Elaborating entity \"series_parallel\" for hierarchy \"change:inst4\|series_parallel:inst1\"" {  } { { "change.bdf" "inst1" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 216 56 208 312 "inst1" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "regb series_parallel.vhd(15) " "Info: (10035) Verilog HDL or VHDL information at series_parallel.vhd(15): object \"regb\" declared but not used" {  } { { "series_parallel.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_parallel.vhd" 15 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fs_out3 change:inst4\|fs_out3:inst9 " "Info: Elaborating entity \"fs_out3\" for hierarchy \"change:inst4\|fs_out3:inst9\"" {  } { { "change.bdf" "inst9" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 456 472 632 552 "inst9" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset fs_out3.vhd(24) " "Warning: VHDL Process Statement warning at fs_out3.vhd(24): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fs_out3.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/fs_out3.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "digit_in fs_out3.vhd(25) " "Warning: VHDL Process Statement warning at fs_out3.vhd(25): signal \"digit_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fs_out3.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/fs_out3.vhd" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "digit fs_out3.vhd(21) " "Warning: VHDL Process Statement warning at fs_out3.vhd(21): signal or variable \"digit\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"digit\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "fs_out3.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/fs_out3.vhd" 21 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "3IN12.bdf 1 1 " "Info: Using design file 3IN12.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 3IN12 " "Info: Found entity 1: 3IN12" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "3IN12 3IN12:inst7 " "Info: Elaborating entity \"3IN12\" for hierarchy \"3IN12:inst7\"" {  } { { "TCM0201.bdf" "inst7" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { 360 1240 1360 552 "inst7" "" } } } }  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "DFF inst8 " "Warning: Block or symbol \"DFF\" of instance \"inst8\" overlaps another block or symbol" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 272 408 472 352 "inst8" "" } } } }  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "DFF inst9 " "Warning: Block or symbol \"DFF\" of instance \"inst9\" overlaps another block or symbol" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 368 408 472 448 "inst9" "" } } } }  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "74151 inst15 " "Warning: Block or symbol \"74151\" of instance \"inst15\" overlaps another block or symbol" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 208 760 880 432 "inst15" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D5 74151 inst15 " "Warning: Port \"D5\" of type 74151 and instance \"inst15\" is missing source signal" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 208 760 880 432 "inst15" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D0 74151 inst15 " "Warning: Port \"D0\" of type 74151 and instance \"inst15\" is missing source signal" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 208 760 880 432 "inst15" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D4 74151 inst15 " "Warning: Port \"D4\" of type 74151 and instance \"inst15\" is missing source signal" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 208 760 880 432 "inst15" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D6 74151 inst15 " "Warning: Port \"D6\" of type 74151 and instance \"inst15\" is missing source signal" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 208 760 880 432 "inst15" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D7 74151 inst15 " "Warning: Port \"D7\" of type 74151 and instance \"inst15\" is missing source signal" {  } { { "3IN12.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/3IN12.bdf" { { 208 760 880 432 "inst15" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/others/maxplus2/74151.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/others/maxplus2/74151.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 74151 " "Info: Found entity 1: 74151" {  } { { "74151.tdf" "" { Text "f:/altera/quartus50/libraries/others/maxplus2/74151.tdf" 11 1 0 } }  } 0}  } {  } 0}