tcm0201.tan.qmsg

在公司做的TCM编解码程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK1 register DEVIDE:inst5\|74393:176\|3 register DEVIDE:inst5\|74393:176\|9 90.91 MHz 11.0 ns Internal " "Info: Clock \"CLK1\" has Internal fmax of 90.91 MHz between source register \"DEVIDE:inst5\|74393:176\|3\" and destination register \"DEVIDE:inst5\|74393:176\|9\" (period= 11.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest register register " "Info: + Longest register to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DEVIDE:inst5\|74393:176\|3 1 REG LC128 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC128; Fanout = 19; REG Node = 'DEVIDE:inst5\|74393:176\|3'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "" { DEVIDE:inst5|74393:176|3 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 176 440 504 256 "3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.800 ns) 6.500 ns DEVIDE:inst5\|74393:176\|9 2 REG LC187 6 " "Info: 2: + IC(3.700 ns) + CELL(2.800 ns) = 6.500 ns; Loc. = LC187; Fanout = 6; REG Node = 'DEVIDE:inst5\|74393:176\|9'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "6.500 ns" { DEVIDE:inst5|74393:176|3 DEVIDE:inst5|74393:176|9 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 43.08 % " "Info: Total cell delay = 2.800 ns ( 43.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns 56.92 % " "Info: Total interconnect delay = 3.700 ns ( 56.92 % )" {  } {  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "6.500 ns" { DEVIDE:inst5|74393:176|3 DEVIDE:inst5|74393:176|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DEVIDE:inst5|74393:176|3 DEVIDE:inst5|74393:176|9 } { 0.000ns 3.700ns } { 0.000ns 2.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 destination 17.200 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1\" to destination register is 17.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns CLK1 1 CLK PIN_125 4 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 4; CLK Node = 'CLK1'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "" { CLK1 } "NODE_NAME" } "" } } { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { 208 -248 -80 224 "CLK1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns DEVIDE:inst5\|74393:175\|9 2 REG LC121 4 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC121; Fanout = 4; REG Node = 'DEVIDE:inst5\|74393:175\|9'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "2.400 ns" { CLK1 DEVIDE:inst5|74393:175|9 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 11.700 ns DEVIDE:inst5\|74393:175\|30 3 REG LC117 6 " "Info: 3: + IC(3.200 ns) + CELL(3.700 ns) = 11.700 ns; Loc. = LC117; Fanout = 6; REG Node = 'DEVIDE:inst5\|74393:175\|30'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "6.900 ns" { DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 744 440 504 824 "30" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.100 ns) 17.200 ns DEVIDE:inst5\|74393:176\|9 4 REG LC187 6 " "Info: 4: + IC(3.400 ns) + CELL(2.100 ns) = 17.200 ns; Loc. = LC187; Fanout = 6; REG Node = 'DEVIDE:inst5\|74393:176\|9'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "5.500 ns" { DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|9 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.600 ns 61.63 % " "Info: Total cell delay = 10.600 ns ( 61.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns 38.37 % " "Info: Total interconnect delay = 6.600 ns ( 38.37 % )" {  } {  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "17.200 ns" { CLK1 DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "17.200 ns" { CLK1 CLK1~out DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|9 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.400ns } { 0.000ns 2.400ns 2.400ns 3.700ns 2.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 17.200 ns - Longest register " "Info: - Longest clock path from clock \"CLK1\" to source register is 17.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns CLK1 1 CLK PIN_125 4 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 4; CLK Node = 'CLK1'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "" { CLK1 } "NODE_NAME" } "" } } { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { 208 -248 -80 224 "CLK1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns DEVIDE:inst5\|74393:175\|9 2 REG LC121 4 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC121; Fanout = 4; REG Node = 'DEVIDE:inst5\|74393:175\|9'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "2.400 ns" { CLK1 DEVIDE:inst5|74393:175|9 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 11.700 ns DEVIDE:inst5\|74393:175\|30 3 REG LC117 6 " "Info: 3: + IC(3.200 ns) + CELL(3.700 ns) = 11.700 ns; Loc. = LC117; Fanout = 6; REG Node = 'DEVIDE:inst5\|74393:175\|30'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "6.900 ns" { DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 744 440 504 824 "30" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.100 ns) 17.200 ns DEVIDE:inst5\|74393:176\|3 4 REG LC128 19 " "Info: 4: + IC(3.400 ns) + CELL(2.100 ns) = 17.200 ns; Loc. = LC128; Fanout = 19; REG Node = 'DEVIDE:inst5\|74393:176\|3'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "5.500 ns" { DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|3 } "NODE_NAME" } "" } } { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 176 440 504 256 "3" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.600 ns 61.63 % " "Info: Total cell delay = 10.600 ns ( 61.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns 38.37 % " "Info: Total interconnect delay = 6.600 ns ( 38.37 % )" {  } {  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "17.200 ns" { CLK1 DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|3 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "17.200 ns" { CLK1 CLK1~out DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|3 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.400ns } { 0.000ns 2.400ns 2.400ns 3.700ns 2.100ns } } }  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "17.200 ns" { CLK1 DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "17.200 ns" { CLK1 CLK1~out DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|9 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.400ns } { 0.000ns 2.400ns 2.400ns 3.700ns 2.100ns } } } { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "17.200 ns" { CLK1 DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|3 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "17.200 ns" { CLK1 CLK1~out DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|3 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.400ns } { 0.000ns 2.400ns 2.400ns 3.700ns 2.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 176 440 504 256 "3" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } }  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "6.500 ns" { DEVIDE:inst5|74393:176|3 DEVIDE:inst5|74393:176|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { DEVIDE:inst5|74393:176|3 DEVIDE:inst5|74393:176|9 } { 0.000ns 3.700ns } { 0.000ns 2.800ns } } } { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "17.200 ns" { CLK1 DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "17.200 ns" { CLK1 CLK1~out DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|9 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.400ns } { 0.000ns 2.400ns 2.400ns 3.700ns 2.100ns } } } { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "17.200 ns" { CLK1 DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|3 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "17.200 ns" { CLK1 CLK1~out DEVIDE:inst5|74393:175|9 DEVIDE:inst5|74393:175|30 DEVIDE:inst5|74393:176|3 } { 0.000ns 0.000ns 0.000ns 3.200ns 3.400ns } { 0.000ns 2.400ns 2.400ns 3.700ns 2.100ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "BS register CODEandIE:inst2\|74161:inst18\|p74161:sub\|9 register series_para_store:inst22\|rega\[11\] 29.59 MHz 33.8 ns Internal " "Info: Clock \"BS\" has Internal fmax of 29.59 MHz between source register \"CODEandIE:inst2\|74161:inst18\|p74161:sub\|9\" and destination register \"series_para_store:inst22\|rega\[11\]\" (period= 33.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.500 ns + Longest register register " "Info: + Longest register to register delay is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CODEandIE:inst2\|74161:inst18\|p74161:sub\|9 1 REG LC57 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC57; Fanout = 29; REG Node = 'CODEandIE:inst2\|74161:inst18\|p74161:sub\|9'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "" { CODEandIE:inst2|74161:inst18|p74161:sub|9 } "NODE_NAME" } "" } } { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { 128 744 808 208 "9" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(4.000 ns) 7.400 ns CODEandIE:inst2\|inst15~36 2 COMB LC53 67 " "Info: 2: + IC(3.400 ns) + CELL(4.000 ns) = 7.400 ns; Loc. = LC53; Fanout = 67; COMB Node = 'CODEandIE:inst2\|inst15~36'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.400 ns" { CODEandIE:inst2|74161:inst18|p74161:sub|9 CODEandIE:inst2|inst15~36 } "NODE_NAME" } "" } } { "CODEandIE.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 768 896 960 816 "inst15" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(1.300 ns) 12.400 ns series_para_store:inst22\|rega\[11\]~226 3 COMB LC161 1 " "Info: 3: + IC(3.700 ns) + CELL(1.300 ns) = 12.400 ns; Loc. = LC161; Fanout = 1; COMB Node = 'series_para_store:inst22\|rega\[11\]~226'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "5.000 ns" { CODEandIE:inst2|inst15~36 series_para_store:inst22|rega[11]~226 } "NODE_NAME" } "" } } { "series_para_store.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_para_store.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 14.500 ns series_para_store:inst22\|rega\[11\] 4 REG LC162 7 " "Info: 4: + IC(0.000 ns) + CELL(2.100 ns) = 14.500 ns; Loc. = LC162; Fanout = 7; REG Node = 'series_para_store:inst22\|rega\[11\]'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "2.100 ns" { series_para_store:inst22|rega[11]~226 series_para_store:inst22|rega[11] } "NODE_NAME" } "" } } { "series_para_store.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_para_store.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 51.03 % " "Info: Total cell delay = 7.400 ns ( 51.03 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 48.97 % " "Info: Total interconnect delay = 7.100 ns ( 48.97 % )" {  } {  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "14.500 ns" { CODEandIE:inst2|74161:inst18|p74161:sub|9 CODEandIE:inst2|inst15~36 series_para_store:inst22|rega[11]~226 series_para_store:inst22|rega[11] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CODEandIE:inst2|74161:inst18|p74161:sub|9 CODEandIE:inst2|inst15~36 series_para_store:inst22|rega[11]~226 series_para_store:inst22|rega[11] } { 0.000ns 3.400ns 3.700ns 0.000ns } { 0.000ns 4.000ns 1.300ns 2.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-14.800 ns - Smallest " "Info: - Smallest clock skew is -14.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BS destination 14.300 ns + Shortest register " "Info: + Shortest clock path from clock \"BS\" to destination register is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns BS 1 CLK PIN_133 30 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_133; Fanout = 30; CLK Node = 'BS'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "" { BS } "NODE_NAME" } "" } } { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { -64 312 480 -48 "BS" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(3.700 ns) 8.300 ns change:inst4\|inst2 2 REG LC3 56 " "Info: 2: + IC(3.400 ns) + CELL(3.700 ns) = 8.300 ns; Loc. = LC3; Fanout = 56; REG Node = 'change:inst4\|inst2'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.100 ns" { BS change:inst4|inst2 } "NODE_NAME" } "" } } { "change.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 112 152 216 192 "inst2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(2.100 ns) 14.300 ns series_para_store:inst22\|rega\[11\] 3 REG LC162 7 " "Info: 3: + IC(3.900 ns) + CELL(2.100 ns) = 14.300 ns; Loc. = LC162; Fanout = 7; REG Node = 'series_para_store:inst22\|rega\[11\]'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "6.000 ns" { change:inst4|inst2 series_para_store:inst22|rega[11] } "NODE_NAME" } "" } } { "series_para_store.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_para_store.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 48.95 % " "Info: Total cell delay = 7.000 ns ( 48.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.300 ns 51.05 % " "Info: Total interconnect delay = 7.300 ns ( 51.05 % )" {  } {  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "14.300 ns" { BS change:inst4|inst2 series_para_store:inst22|rega[11] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.300 ns" { BS BS~out change:inst4|inst2 series_para_store:inst22|rega[11] } { 0.000ns 0.000ns 3.400ns 3.900ns } { 0.000ns 1.200ns 3.700ns 2.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BS source 29.100 ns - Longest register " "Info: - Longest clock path from clock \"BS\" to source register is 29.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns BS 1 CLK PIN_133 30 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_133; Fanout = 30; CLK Node = 'BS'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "" { BS } "NODE_NAME" } "" } } { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { -64 312 480 -48 "BS" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(3.700 ns) 8.300 ns change:inst4\|inst2 2 REG LC3 56 " "Info: 2: + IC(3.400 ns) + CELL(3.700 ns) = 8.300 ns; Loc. = LC3; Fanout = 56; REG Node = 'change:inst4\|inst2'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.100 ns" { BS change:inst4|inst2 } "NODE_NAME" } "" } } { "change.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 112 152 216 192 "inst2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(3.700 ns) 15.900 ns CODEandIE:inst2\|74161:inst18\|p74161:sub\|8 3 REG LC58 28 " "Info: 3: + IC(3.900 ns) + CELL(3.700 ns) = 15.900 ns; Loc. = LC58; Fanout = 28; REG Node = 'CODEandIE:inst2\|74161:inst18\|p74161:sub\|8'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.600 ns" { change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 } "NODE_NAME" } "" } } { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { 288 744 808 368 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(4.000 ns) 23.300 ns CODEandIE:inst2\|inst15~36 4 COMB LC53 67 " "Info: 4: + IC(3.400 ns) + CELL(4.000 ns) = 23.300 ns; Loc. = LC53; Fanout = 67; COMB Node = 'CODEandIE:inst2\|inst15~36'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.400 ns" { CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 } "NODE_NAME" } "" } } { "CODEandIE.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 768 896 960 816 "inst15" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.100 ns) 29.100 ns CODEandIE:inst2\|74161:inst18\|p74161:sub\|9 5 REG LC57 29 " "Info: 5: + IC(3.700 ns) + CELL(2.100 ns) = 29.100 ns; Loc. = LC57; Fanout = 29; REG Node = 'CODEandIE:inst2\|74161:inst18\|p74161:sub\|9'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "5.800 ns" { CODEandIE:inst2|inst15~36 CODEandIE:inst2|74161:inst18|p74161:sub|9 } "NODE_NAME" } "" } } { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { 128 744 808 208 "9" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 50.52 % " "Info: Total cell delay = 14.700 ns ( 50.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.400 ns 49.48 % " "Info: Total interconnect delay = 14.400 ns ( 49.48 % )" {  } {  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "29.100 ns" { BS change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 CODEandIE:inst2|74161:inst18|p74161:sub|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "29.100 ns" { BS BS~out change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 CODEandIE:inst2|74161:inst18|p74161:sub|9 } { 0.000ns 0.000ns 3.400ns 3.900ns 3.400ns 3.700ns } { 0.000ns 1.200ns 3.700ns 3.700ns 4.000ns 2.100ns } } }  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "14.300 ns" { BS change:inst4|inst2 series_para_store:inst22|rega[11] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.300 ns" { BS BS~out change:inst4|inst2 series_para_store:inst22|rega[11] } { 0.000ns 0.000ns 3.400ns 3.900ns } { 0.000ns 1.200ns 3.700ns 2.100ns } } } { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "29.100 ns" { BS change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 CODEandIE:inst2|74161:inst18|p74161:sub|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "29.100 ns" { BS BS~out change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 CODEandIE:inst2|74161:inst18|p74161:sub|9 } { 0.000ns 0.000ns 3.400ns 3.900ns 3.400ns 3.700ns } { 0.000ns 1.200ns 3.700ns 3.700ns 4.000ns 2.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { 128 744 808 208 "9" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "series_para_store.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/series_para_store.vhd" 15 -1 0 } }  } 0}  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "14.500 ns" { CODEandIE:inst2|74161:inst18|p74161:sub|9 CODEandIE:inst2|inst15~36 series_para_store:inst22|rega[11]~226 series_para_store:inst22|rega[11] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CODEandIE:inst2|74161:inst18|p74161:sub|9 CODEandIE:inst2|inst15~36 series_para_store:inst22|rega[11]~226 series_para_store:inst22|rega[11] } { 0.000ns 3.400ns 3.700ns 0.000ns } { 0.000ns 4.000ns 1.300ns 2.100ns } } } { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "14.300 ns" { BS change:inst4|inst2 series_para_store:inst22|rega[11] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.300 ns" { BS BS~out change:inst4|inst2 series_para_store:inst22|rega[11] } { 0.000ns 0.000ns 3.400ns 3.900ns } { 0.000ns 1.200ns 3.700ns 2.100ns } } } { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "29.100 ns" { BS change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 CODEandIE:inst2|74161:inst18|p74161:sub|9 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "29.100 ns" { BS BS~out change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 CODEandIE:inst2|74161:inst18|p74161:sub|9 } { 0.000ns 0.000ns 3.400ns 3.900ns 3.400ns 3.700ns } { 0.000ns 1.200ns 3.700ns 3.700ns 4.000ns 2.100ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "FS_IN " "Info: No valid register-to-register data paths exist for clock \"FS_IN\"" {  } {  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "BS 39 " "Warning: Circuit may not operate. Detected 39 non-operational path(s) clocked by clock \"BS\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "CODEandIE:inst2\|74161:inst18\|p74161:sub\|9 CODEandIE:inst2\|74161:inst18\|p74161:sub\|9 BS 8.4 ns " "Info: Found hold time violation between source  pin or register \"CODEandIE:inst2\|74161:inst18\|p74161:sub\|9\" and destination pin or register \"CODEandIE:inst2\|74161:inst18\|p74161:sub\|9\" for clock \"BS\" (Hold time is 8.4 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "14.800 ns + Largest " "Info: + Largest clock skew is 14.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BS destination 29.100 ns + Longest register " "Info: + Longest clock path from clock \"BS\" to destination register is 29.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns BS 1 CLK PIN_133 30 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_133; Fanout = 30; CLK Node = 'BS'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "" { BS } "NODE_NAME" } "" } } { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { -64 312 480 -48 "BS" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(3.700 ns) 8.300 ns change:inst4\|inst2 2 REG LC3 56 " "Info: 2: + IC(3.400 ns) + CELL(3.700 ns) = 8.300 ns; Loc. = LC3; Fanout = 56; REG Node = 'change:inst4\|inst2'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.100 ns" { BS change:inst4|inst2 } "NODE_NAME" } "" } } { "change.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 112 152 216 192 "inst2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(3.700 ns) 15.900 ns CODEandIE:inst2\|74161:inst18\|p74161:sub\|8 3 REG LC58 28 " "Info: 3: + IC(3.900 ns) + CELL(3.700 ns) = 15.900 ns; Loc. = LC58; Fanout = 28; REG Node = 'CODEandIE:inst2\|74161:inst18\|p74161:sub\|8'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.600 ns" { change:inst4|inst2 CODEandIE:inst2|74161:inst18|p74161:sub|8 } "NODE_NAME" } "" } } { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { 288 744 808 368 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(4.000 ns) 23.300 ns CODEandIE:inst2\|inst15~36 4 COMB LC53 67 " "Info: 4: + IC(3.400 ns) + CELL(4.000 ns) = 23.300 ns; Loc. = LC53; Fanout = 67; COMB Node = 'CODEandIE:inst2\|inst15~36'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201.quartus_db" { Floorplan "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/" "" "7.400 ns" { CODEandIE:inst2|74161:inst18|p74161:sub|8 CODEandIE:inst2|inst15~36 } "NODE_NAME" } "" } } { "CODEandIE.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 768 896 960 816 "inst15" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.100 ns) 29.100 ns CODEandIE:inst2\|74161:inst18\|p74161:sub\|9 5 REG LC57 29 " "Info: 5: + IC(3.700 ns) + CELL(2.100 ns) = 29.100 ns; Loc. = LC57; Fanout = 29; REG Node = 'CODEandIE:inst2\|74161:inst18\|p74161:sub\|9'" {  } { { "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" "" { Report "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/db/TCM0201_cmp.qrpt" Compiler "TCM0201" "UNKNOWN" "V1" "E