tcm0201.tan.qmsg

在公司做的TCM编解码程序

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "change:inst4\|parallel_series:inst\|digit\[2\]~124 " "Info: Node \"change:inst4\|parallel_series:inst\|digit\[2\]~124\"" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "change:inst4\|parallel_series:inst5\|digit\[4\]~120 " "Info: Node \"change:inst4\|parallel_series:inst5\|digit\[4\]~120\"" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "change:inst4\|parallel_series:inst5\|digit\[0\]~116 " "Info: Node \"change:inst4\|parallel_series:inst5\|digit\[0\]~116\"" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "change:inst4\|parallel_series:inst\|digit\[4\]~120 " "Info: Node \"change:inst4\|parallel_series:inst\|digit\[4\]~120\"" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "change:inst4\|parallel_series:inst\|digit\[6\]~116 " "Info: Node \"change:inst4\|parallel_series:inst\|digit\[6\]~116\"" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 22 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "RST " "Info: Assuming node \"RST\" is an undefined clock" {  } { { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { 128 -256 -88 144 "RST" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RST" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK1 " "Info: Assuming node \"CLK1\" is an undefined clock" {  } { { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { 208 -248 -80 224 "CLK1" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "BS " "Info: Assuming node \"BS\" is an undefined clock" {  } { { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { -64 312 480 -48 "BS" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "BS" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "FS_IN " "Info: Assuming node \"FS_IN\" is an undefined clock" {  } { { "TCM0201.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/TCM0201.bdf" { { 40 296 464 56 "FS_IN" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FS_IN" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "change:inst4\|parallel_series:inst\|fs " "Info: Detected ripple clock \"change:inst4\|parallel_series:inst\|fs\" as buffer" {  } { { "parallel_series.vhd" "" { Text "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/parallel_series.vhd" 9 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "change:inst4\|parallel_series:inst\|fs" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "DEVIDE:inst5\|74393:176\|9 " "Info: Detected ripple clock \"DEVIDE:inst5\|74393:176\|9\" as buffer" {  } { { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DEVIDE:inst5\|74393:176\|9" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "7492:inst18\|7 " "Info: Detected ripple clock \"7492:inst18\|7\" as buffer" {  } { { "7492.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/7492.bdf" { { 144 544 608 224 "7" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "7492:inst18\|7" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "DEVIDE:inst5\|74393:176\|3 " "Info: Detected ripple clock \"DEVIDE:inst5\|74393:176\|3\" as buffer" {  } { { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 176 440 504 256 "3" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DEVIDE:inst5\|74393:176\|3" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "DEVIDE:inst5\|74393:175\|30 " "Info: Detected ripple clock \"DEVIDE:inst5\|74393:175\|30\" as buffer" {  } { { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 744 440 504 824 "30" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DEVIDE:inst5\|74393:175\|30" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "DEVIDE:inst5\|74393:175\|9 " "Info: Detected ripple clock \"DEVIDE:inst5\|74393:175\|9\" as buffer" {  } { { "74393.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DEVIDE:inst5\|74393:175\|9" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "CODEandIE:inst2\|74161:inst18\|p74161:sub\|8 " "Info: Detected ripple clock \"CODEandIE:inst2\|74161:inst18\|p74161:sub\|8\" as buffer" {  } { { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { 288 744 808 368 "8" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CODEandIE:inst2\|74161:inst18\|p74161:sub\|8" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "CODEandIE:inst2\|inst15~36 " "Info: Detected gated clock \"CODEandIE:inst2\|inst15~36\" as buffer" {  } { { "CODEandIE.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/CODEandIE.bdf" { { 768 896 960 816 "inst15" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CODEandIE:inst2\|inst15~36" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "CODEandIE:inst2\|74161:inst18\|p74161:sub\|9 " "Info: Detected ripple clock \"CODEandIE:inst2\|74161:inst18\|p74161:sub\|9\" as buffer" {  } { { "p74161.bdf" "" { Schematic "f:/altera/quartus50/libraries/others/maxplus2/p74161.bdf" { { 128 744 808 208 "9" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CODEandIE:inst2\|74161:inst18\|p74161:sub\|9" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "change:inst4\|inst2 " "Info: Detected ripple clock \"change:inst4\|inst2\" as buffer" {  } { { "change.bdf" "" { Schematic "E:/project/VB编译码程序可用070214/VB编码程序（CPLD1模块）/TCM070119/change.bdf" { { 112 152 216 192 "inst2" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "change:inst4\|inst2" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "RST " "Info: No valid register-to-register data paths exist for clock \"RST\"" {  } {  } 0}